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RF6001
Rev A3 DS050929
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Part of the POLARIS™ TOTAL RADIO™ Solution
RX Blanking (BLANK) - Address 110011
DELAY - Address 110100
TX Data Control (DFILL) - Address 110101
Location
Bit Name
Default
Function
BLANK (17)
MSR
0
Controls the behavior of the MS pulse in a GPRS serial TX burst, if the RF6001 is the bus
master. If MSR is high, then an MS pulse will occur every 16MCK clock pulse, even
between GPRS bursts. If MSR is low, the MS pulse will appear with the first MCK
pulse of each burst, regardless of how MCK pulses have elapsed since the last MS
pulse.
0=MS resume disabled
1=MS resume enabled
BLANK (16:14)
G_CNT(2:0)
000
This field allows variable blanking of user data bits.
In FIFO, this bit is only active in MS PULSE mode (TXF=2). On the rising edge of MS, the
FIFO will ignore the first GCNT bits on the serial interface. In TX serial mode, the
GMSK differential encoder and modulator will ignore the first GCNT bits. During this
time, G_DEF will be gated to the modulator. In GPRS mode, GCNT is only active in
the first burst.
BLANK (13)
DE_INIT
0
Power on default of the differential encoder starting value.
BLANK (12)
reserved
0
reserved, program to zero (0).
BLANK (11:6)
BLK_DLY(5:0)
18h
Channel filter blanking delay. Delay=BLK_DLY*3.69us.
BLANK (5:0)
AGC_DLY(5:0)
26h
RX output blanking delay. Delay=AGC_DLY*3.69us.
Location
Bit Name
Default
Function
DELAY (17)
ADEN_2
1
Second DC Correction System Enable
DELAY (16)
AD2EN_2
1
Second DC Correction System Enable 2
0=DC correction system will continue to operate after the adapt time is elapsed, at
the rate defined by ADCLK.
1=DC correction will stop at the end of the adapt time.
DELAY (15:14)
ADCCLK_2
(1:0)
11
DC Correction System Clock Rate, after adapt time is elapsed. Default is 13MHz/48, for
slowest adapt.
00=13MHz
01=13MHz/2
10=13MHz/24
11=13MHz/48
DELAY (13:8)
DCAD_2(5:0)
25h
Fine DC correction fast adapt time. Programs in steps of (48/13)us. Default is 70us.
DELAY (7:0)
reserved
0
reserved, program to zero (0).
Location
Bit Name
Default
Function
DFILL (17)
FCLR
0
If FCLR is set high, the FIFO will be cleared. Once the operation is complete, the SDI bit
will automatically revert low.
DFILL (16)
G_DEF
0
G_DEF is the input value to the GMSK modulator when the modulator data input is not
active.
DFILL (15)
reserved
0
reserved, program to zero (0).
DFILL (14:10)
G_DLY(4:0)
0
This field will increase the latency of the GMSK modulator in 1/16 symbol increments.
The modulator delay can be adjusted from 12.2 quarter symbol times (qst) to
19.95qst. G_DLY cannot be used without EALGN.
DFILL (9:5)
RD_DLY(4:0)
0
In UAM mode, RD_DLY can be used to delay the ramp down in 1/8S increments, relative
to the falling edge of TXST. This field is not used if UAM is low.
DFILL (4:0)
RU_DLY(4:0)
0
In UAM mode, RU_DLY can be used to delay the ramp up in 1/8S increments, relative to
the rising edge of TXST. Note that this field is only used in GPRS mode because PAT
always controls the first ramp up delay.
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