40 of 70
RF6001
Rev A3 DS050929
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
Part of the POLARIS™ TOTAL RADIO™ Solution
GMSK Ramp-Up
The diagram below presents the ramp up for GMSK in the FIFO mode of operation. The latency is the sum of G_DLY and the
basic GMSK latency of 12qst. The sum of the two is 18qst and is selected to match the 8PSK latency in this example. Any
glitch will occur when the clock resets at the end of G_DLY and thus is at a low power level. This allows G_DEF to be used for
the guard bits if desired. (Note that 8qst ramps have been used for these examples; 13qst or 16qst ramps could be used
equally well.)
If data is loaded with the serial mode system using MS, then the diagram below presents the operation of the system.
TX_EN is set to occur 18qst before the top of the ramp so as to not violate the ETSI time mask at the -30dBc point. MD_DLY1
is set to start the modulator 66qst plus G_DLY before TX_EN so that the first valid data symbol is the first tail symbol. G_CNT
will have to be set to one in this case so that the initial state of the differential encoder is set at the correct time. If the base-
band differential encoding is used then G_CNT does not matter.
Note that the user could also send the guard symbols if MD_DLY1 is further advanced.
Since the new data flow starts well in advance of the burst, then there should be no issue with phase transitions if the delay
from the rise of TX_ST to the end of MD_DLY1 is not an integer number of symbol times. Any such transition will occur at mini-
mum output power levels if MD_DLY1 is advanced far enough.
PAT
TXST
DAC1
TXEN
PA Turns ON
tail
tail
tail
Top of Ramp
2qst
Modulator
Start
16qst
First data
from FIFO
clocks reset
12qst
Latency of GMSK
mod complete
TXENU
MD_DLY1
G_DLY
G_DEF
Data
at RF
FIFO GMSK Start-up Mode, EALGN=1
PAT
TXST
DAC1
TXEN
PA Turns ON
tail
tail
tail
Top of Ramp
2qst
Modulator
Start
MCK starts
18qst
max
MCK
MS
First valid data
from baseband
6qst
12qst
Latency of GMSK
mod complete
TXENU
MD_DLY
First MS pulse is
always blanked
16 MCKs
64qst
G_DLY
Modulator clock resets
G_DLY
G_DEF
Data
at RF
Serial GMSK Mode using MS, MCK and MS are Output from RF6001, EALGN=1
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
