TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
GSIO PORT
Preliminary
11-3
GSIOn Control Register (GSCR0 ~ GSCR3)
0x80000708 + (0x10 * n)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
EN
MS
WORD
WS
DIV
CP
CM
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
DELAY
FP
FRM1
FRM2
EN [31]
GSIO Enable
0
Disable the corresponding GSIO block
1
Enable the corresponding GSIO block
MS [30]
First Bit Select
0
Data is transmitted or received by LSB first order
1
Data is transmitted or received by MSB first order
WORD [29:26]
GSIO word size
n
GSIO data transaction has (n+1) bit unit, n = 0 ~ 15
*) This is valid only when the WS bit of GSCRn register is 0.
WS [25]
Word Size Select
0
GSIO word size is determined by WORD of GSCRn register
1
GSIO word size is determined by BW of GSDO register
DIV [24:18]
GSIO base clock speed control
0
Reserved.
1
≤ n ≤ 127
GSIO base clock has 1/(2n+2) of GCLK frequency.
CP [17]
GSIO clock polarity
0
SDO changes or SDI is sampled at SCK falling
1
SDO changes or SDI is sampled at SCK rising
CM [16]
Last clock mask
0
No mask. GSIO clock is generated for every SDO.
1
GSIO clock is masked at the last SDO period.
DELAY [14:13]
Initial delay for serial transmission
0
Reserved. DELAY should not be set to 0.
1
≤ n ≤ 3
GSIO transmission starts after n base clock has generated.
FP [12]
Frame pulse polarity
0
FRM has low active pulse
1
FRM has high active pulse
FRM1 [11:6]
Frame pulse start position
n
Frame pulse starts after n base clock has generated
FRM2 [5:0]
Frame pulse end position
n
Frame pulse ends after n base clock has generated
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
