TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
GSIO PORT
Preliminary
11-1
11 GSIO PORT
11.1 Overview
The TCC76x has four GSIOs (General Purpose Serial Input/Output) for communication
between the TCC76x and other devices that have serial interface. All the pins in the
GSIOs are multiplexed with GPIOs. Refer the chapter of GPIO for more information
about these multiplexing. User can program what these multiplexed pins are used for.
The GSIO block has 4 pins.
SDO
the serial data output pin
SDI
the serial data input pin
SCK
the serial clock pin
FRM
the frame pin
The base clock is generated dividing the GCLK by programming the GSIO control
register GSCR. The SCK is generated from the basic clock in every data transfers.
Using GSIO control field in the GSCR can program various types of serial interface.
There are 5 control registers for GSIOs; GSCR0, GSCR1, GSCR2, GSCR3, and GSICR.
The start time of transfer can be controlled with programming the delay counter field in
the GSCRn. The base counter increments at every base clock right after writing the data
into the GSDRn. The serial data starts to come out when delay counter value are same
to base counter value. The word size of transfer can be programmed from 1 bit to 16
bits. The frame1 and the frame2 fields specify the start and end point of transition based
on base counter. The frame polarity defines whether the frame signal is low active or
high active signal. The Last Clock mask filed is for special serial interface, which makes
the last clock pulse masked.
/2
n Divider
Counter
Frame
Coparator
SCK
Generator
GSFC
GSDO
GSCR
base_clk
frame1, frame2
SDO
SCK
FRM
divider factor n
word_size
SDI
GSDI
GCLK
SIPO
SIPO
Figure 11.1 GSIO Block Diagram
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