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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
UART/IRDA
Preliminary
10-5
UART/IrDA Control Register (UTCR)
0x8000060C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
NO
BK
TF
RF
FIFO
PR
ST
0
NO [9]
Type
Start Bit Width Check
0
Check if the pulse width of start bit is more than 0.5 bit
duration of baud rate
1
R/W
Don’t check the pulse width of start bit (test or boot
mode only)
BK [8]
Type
Break Control Bit
0
Normal operation
1
R/W
Bit ‘0’ is transmitted regardless of THR
TF [7]
Type
Reset Transmitter FIFO
1
R/W
The transmitter FIFO is cleared
RF [6]
Type
Reset Receiver FIFO
1
R/W
The receiver FIFO is cleared
FIFO [5:4]
Type
RX FIFO Level Select
n
R/W
0 = 1byte FIFO,
1 = 2 byte FIFO
2 = 4 byte FIFO,
3 = 7 byte FIFO
If this field is set to 1, it means that the RDA flag or interrupt is influenced when the
number of received data in the RX FIFO is 2. It is recommended that this field is set to 0,
so right after reception of some data, the RDA flag or interrupt can be generated.
PR [3:2]
Type
Parity Bit Select
0
Even parity
1
Odd parity
2, 3
R/W
Parity is disabled
ST [1]
Type
Stop Bit
0
1 Stop bit
1
R/W
2 Stop bit
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