TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
DMA CONTROLLER
Preliminary
13-2
13.2 Register Description
Table 13.1 DMA Controller Register Map (Base Address = 0x80000E00)
Name
Address
Type
Reset
Description
ST_SADR0
0x00
R/W
-
StartAddress of Source Block
SPARAM0
0x04/0x08
R/W
-
Parameter of Source Block
C_SADR0
0x0C
R
-
CurrentAddress of Source Block
ST_DADR0
0x10
R/W
-
StartAddress of Destination Block
DPARAM0
0x14/0x18
R/W
-
Parameter of Destination Block
C_DADR0
0x1C
R
-
CurrentAddress of Destination Block
HCOUNT0
0x20
R/W
0x00000000
Initial and Current Hop count
C
H
A
N
N
E
L
0
CHCTRL0
0x24
R/W
0x00000000
Channel Control Register
CHCONFIG
0x2C
R/W
-
Channel Configuration Register
ST_SADR1
0x30
R/W
-
StartAddress of Source Block
SPARAM1
0x34/0x38
R/W
-
Parameter of Source Block
C_SADR1
0x3C
R
-
CurrentAddress of Source Block
ST_DADR1
0x40
R/W
-
StartAddress of Destination Block
DPARAM1
0x44/0x48
R/W
-
Parameter of Destination Block
C_DADR1
0x4C
R
-
CurrentAddress of Destination Block
HCOUNT1
0x50
R/W
0x00000000
Initial and Current Hop count
C
H
A
N
N
E
L
1
CHCTRL1
0x54
R/W
0x00000000
Channel Control Register
Start Source Address Register (ST_SADR)
0x80000E00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ST_SADR[31:16]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ST_SADR[15:0]
This register contains the start address of source memory block for DMA transfer. The transfer
begins reading data from this address.
Start Destination Address Register (ST_DADR)
0x80000E10
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ST_DADR[31:16]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ST_DADR[15:0]
This register contains the start address of destination memory block for DMAtransfer.
Source Block Parameter Register (SPARAM)
0x80000E04 / 0x80000E08
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SMASK[23:8]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SMASK[7:0]
SINC[7:0]
SMASK [31:8]
Source Address Mask Register
0
non-masked
1
Masked so that source address bit doesn’t be changed during DMA
transfer
Each bit field controls the dedicated bit of source address field. That is, if SMASK[23] is set to 1,
the 28th bit of source address is masked, and if SMASK[22] is set to 1, the 27th bit of source
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