TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
DMA CONTROLLER
Preliminary
13-4
HOP Count Register (HCOUNT)
0x80000E20
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
C_HCOUNT[15:0]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ST_HCOUNT[15:0]
C_HCNT [31:16]
Type
Current Hop Count
cn
R
Represent cn number of Hop transfer remains
ST_HCNT [15:0]
Type
Start Hop Count
sn
R/W
DMAtransfers data by amount of sn Hop transfers
At the beginning of transfer, the C_HCNT is updated by ST_HCNT register. At the end of every
hop transfer, this is decremented by 1 until it reaches to zero. When this reaches to zero, the DMA
finishes its transfer and may or may not generate its interrupt according to IEN flag of CHCTRL
register.
Channel Control Register (CHCTRL)
0x80000E24
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
DMASEL[12:0]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CONT
0
SYNc
HRD
LOCK
BST
TYPE
BSIZE
WSIZE
FLAG
IEN
REP
EN
DMASEL [28:16]
Select Source of DMA Request
non-zero
Each bit field selects corresponding signal as a source for DMA
request. The bit-map of this register is identical with the IEN of
interrupt controller. So if you want to use EXINT0 pin as a source of
DMA request, set DMASEL[0] as 1 and select transfer type of
HW_ARBIT or HW_BURST.
If multiple bits of this field are set, all the corresponding signal can
generate DMArequest for this channel.
CONT [15]
Issue Continuous Transfer
0
DMA transfer begins from ST_SADR / ST_DADR address
1
DMAtransfer begins from C_SADR / C_DADR address
It must be used after the former transfer has been executed, so that
C_SADR and C_DADR contain a meaningful value.
SYNC [13]
Hardware Request Synchronization
0
Do not Synchronize Hardware Request.
1
Synchronize Hardware Request.
HRD [12]
Hardware Request Direction
0
ACK/EOT signals are issued when DMA-Read Operation.
1
ACK/EOT signals are issued When DMA-Write Operation.
LOCK [11]
Issue Locked Transfer
1
DMAtransfer executed with lock transfer
Lock field controls the LOCK signal (refer toAHB specification). When the LOCK is set to 1,
the DMAtransfer doesn’t be bothered by otherAHB masters like LCD controller,ARM etc. This
field is only meaningful in case of non-burst type transfers.
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