TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
DMA CONTROLLER
Preliminary
13-3
address is masked, and so on. If a bit is masked, a corresponding bit of address bus is not changed
during DMAtransfer. This function can be used to generate circular buffer address.
SINC [7:0]
Source Address Increment Register
sinc
Source address is added by amount of sinc at every write cycles. sinc is
represented as 2’s complement, so if SINC[7] is 1, the source address is
decremented.
The addresses of DMA transfer have 32bit wide, but the upper 4bit of them are not affected
during DMAtransfer. If the source or destination address reaches its maximum address space like
0x7FFFFFFF or 0x2FFFFFFF, the next transfer is starting from 0x70000000 or 0x20000000 not
from 0x80000000 or 0x30000000.
Destination Block Parameter Register (DPARAM)
0x80000E14 / 0x80000E18
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DMASK[23:8]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMASK[7:0]
DINC[7:0]
DMASK [23:8]
Destination Address Mask Register
0
non-masked
1
Masked so that destination address bit doesn’t be changed during DMA
transfer
Each bit field controls the corresponding bit of source address field. That is, if DMASK[23] is set
to 1, the 28th bit of source address is masked, and if DMASK[22] is set to 1, the 27th bit of
source address is masked, and so on. If a bit is masked, a corresponding bit of address bus is not
changed during DMAtransfer. This function can be used to generate circular buffer address.
DINC [7:0]
Destination Address Increment Register
dinc
Destination address is added by amount of dinc at every write cycles.
dinc is represented as 2’s complement, so if DINC[7] is 1, the
destination address is decremented.
The addresses of DMA transfer have 32bit wide, but the upper 4bit of them are not affected
during DMAtransfer. If the source or destination address reaches its maximum address space like
0x7FFFFFFF or 0x2FFFFFFF, the next transfer is starting from 0x70000000 or 0x20000000 not
from 0x80000000 or 0x30000000.
Current Source Address Register (C_SADR)
0x80000E0C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
C_SADR[31:16]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C_SADR[15:0]
This register contains the current source address of DMA transfer. It represents that the current
transfer read data from this address. This is read only register.
Current Destination Address Register (C_DADR)
0x80000E1C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
C_DADR[31:16]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C_DADR[15:0]
This register contains current destination address of DMA transfer. It represents that the current
transfer write data to this address. This is read only register.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
