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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
DMA CONTROLLER
Preliminary
13-6
1HOP
WAIT
1HOP
WAIT
1HOP
WAIT
IDLE
< SINGLE TRANSFER with edge-triggered >
1HOP
WAIT
1HOP
1HOP
WAIT
IDLE
< SINGLE TRANSFER with Level Sensitive >
1HOP
WAIT
WAIT
< S(H)W TRANSFER with ARBitration >
1HOP
IDLE
WAIT
1HOP
WAIT
1HOP
WAIT
1HOP
WAIT
1HOP
< S(H)W TRANSFER with Burst >
IDLE
1HOP
1HOP
1HOP
1HOP
1HOP
1HOP
1HOP
EREQ
Transefer
EREQ
Transefer
Transefer
Transefer
Figure 13.3 The Example Of Various Types of Transfer.
BSIZE [7:6]
Burst Size
0
1 Burst transfer consists of 1 read or write cycle.
1
1 Burst transfer consists of 2 read or write cycles
2, 3
1 Burst transfer consists of 4 read or write cycles
WSIZE [5:4]
Word Size
0
Each cycle read or write 8bit data
1
Each cycle read or write 16bit data
2, 3
Each cycle read or write 32bit data
FLAG [3]
Type
DMA Done Flag
1
R
Represents that all hop of transfers are fulfilled.
1
W
Clears FLAG to 0
It does not automatically cleared by another transfer starts, so before starting any other DMA
transfer, user must clear this flag to 0 for checking DMAstatus correctly.
IEN [2]
Interrupt Enable
1
At the same time the FLAG goes to 1, DMA interrupt request
is generated.
To generate IRQ or FIQ interrupt, the DMA flag of IEN register in the interrupt controller must
be set to 1 ahead.
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