TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
LCD CONTROLLER
Preliminary
14-2
The following key parameters can be programmed:
horizontal front and back porch
horizontal synchronization pulse width
number of panel clocks per line
vertical front and back porch
vertical synchronization pulse width
number of lines per panel
signal polarity
panel clock frequency
AC panel bias
STN mono 1, 2, 4bpp
STN color 8bpp(palletized, 256colors from 3375), 16bpp(direct 4:4:4RGB)
STN 4 or 8-bit interface mode
TFT LCD
NTSC/PAL, Interlace/Non-interlace mode
YUV2RGB, RGB2YUV
Encoded pixel data are stored in off-chip memory in the frame buffer and are transferred
to the LCDC’s input FIFO, on a demand basis, using the AMBAAHB master interface.
The LCDC issues a service request to the DMA after it has been initialized and enabled.
The DMA automatically performs burst word transfers, filling empty entries of the FIFO.
Values are fetched from the bottom of the FIFO, one entry at a time, and each 32-bit value
is unpacked into individual pixel encodings, of 1, 2, 4, 8 or 16 bits each. After value is
removed from the FIFO, the entries are invalidated.
The frame buffer is in an off-chip memory area used to supply enough encoded pixel
values to fill the entire screen one or more times. The pixel data buffer contains one
encoded pixel values for each of the pixels present on the screen. The number of pixel
data values depends on the size of the screen. Figure 14.4 shows the memory
organization within the frame buffer for each size pixel encoding.
14.2 Related Blocks
Before using LCDC, it needs to configure blocks which are related to LCDC.
First, timing control signals and pixel data signals of LCDC use GPIO_B[20:17] and
GPIO_A[31:16]. Figure 14.2 shows GPIO mapping. Therefore, these GPIO ports
must be configured to LCD function and output mode. GPIO part explains these
configurations in detail. Figure 14.3 shows output pixel data organization on
GPIO[31:16].
Second, LCLK, which is the main clock of LCDC, must be enabled and configured to
the proper frequency. HCLK frequency must be higher than LCLK frequency.
Otherwise, FIFO underrun is occurred. In case of FIFO underrun, HCLK frequency
must be set to faster value and/or LCLK frequency must be set to slower value.
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