TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
LCD CONTROLLER
Preliminary
14-4
14.4 STN LCD
The LCDC generates VSYNC, HSYNC, PXCLK, ACBIAS, and PXDATA signals for STN LCD
driver.
Figure 14.4 shows 1bpp, 2bpp, 4bpp, 8bpp, and 16bpp of PXDATA memory
organization. BR of LCTRL register indicates whether pixel data in frame memory is big-
endian for 1bpp, 2bpp, or 4bpp mode. Figure 14.5 shows RGB configuration for color
STN LCD.
The timing diagram for STN mode is shown in Figure 14.7. VSYNC and HSYNC pulse
are controlled by the configurations of the LPC field of LHTIME and FLC field of
LVTIME1 and LVTIME2. Each field is related to the LCD size and display mode.
In 1bpp, 2bpp, 4bpp:
LPC
=(Horizontal display size / pixel data width) – 1
In 8pp and 16bpp (RGB):
LPC
= {3 * Horizontal display size / (pixel data width) – 1}
Pixel data width is determined by PXDW of LCTRL register. In the case of STN LCD
mode, it must be 4 or 8-bit width.
31
p31
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16
p8
p9
p10
p11
p12
p13
p14
p15
p4
p5
p6
p7
p2
p3
p1
15
p15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0
p0
p1
p2
p3
p4
p5
p6
p7
p0
p1
p2
p3
p0
p1
p0
2BPP
1BPP
4BPP
8BPP
16BPP
2BPP
1BPP
4BPP
8BPP
16BPP
a) BR=0
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