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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
LCD CONTROLLER
Preliminary
14-8
Example
For a monochrome STN LCD, 4-bit interface panel, 4 pixels are captured by the
panel in every panel clock cycle. Figure 14.8 gives the major registers to be
programmed for supporting 4-bit interface STN LCD. LCLK and Refresh rate are
examples only. And LSWC, LEWC, LPW, and FEWC are STN LCD panel
dependent.
LCLK = 20 MHz, Refresh rate = 60 Hz
PXDW* = 0 (4bits)
VD* = 1
BPP* = 2 (4bpp)
DP* = 0 (one pixel data per pixel clock cycle)
NI = 1
TV* = 0, TFT* = 0, STN* = 1
LSWC* = LEWC* = LPW* = FEWC* = 1 (STN LCD dependent)
Width
(pixel)
Height
(pixel)
LPC*
FLC*
DHSIZE* DVSIZE*
F**
PXCLK_REQ
CLKDIV* fPXCLK
***
160
160
39
159
160
160
0.393
25
0.4
160
200
39
199
160
200
0.491
20
0.5
320
200
79
199
320
200
0.973
10
1
.*) control registers to be programmed. **) Refer to expression (2). ***) Refer to expression (1).
Figure 14.8 Monochrome STN LCD(4bits, 1BPP) example
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