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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
LCD CONTROLLER
Preliminary
14-11
14.6 NTSC/PAL interface
The LCDC can generate the control signals for 8-bit or 16-bit NTSC/PAL encoder. The
pixel color mapping of NTSC/PAL mode is identical to that of 8-bit or 16-bit LCD
interfacing.
For NTSC/PAL interface, TV field of LCTRL register must be set. Registers used in this
mode are similar to those in TFT mode except for LVTIME1 and LVTIME2 registers.;
LVTIME1 is for odd field and LVTIME2 is for Even field. And these registers value is
not based on HSYNC, but based on half of HSYNC. For example, if FPW of LVTIME1
is 3, pulse width of VSYNC on odd field is not 4 HSYNC cycles, but 2 HSYNC cycles.
And if FPW of LVTIME1 is 4, it represents to 2.5 HSYNC cycles.
Interlace/Non-interlace mode can be configured by NI field of LCTRL register. Figure
14.13 and Figure 14.14 each show the timing diagram of NTSC and PAL interlace mode.
In non-interlace mode, odd field sync signals are repeated instead.
VSYNC
HSYNC
(LVTIME1.FPW +1)/2
Odd Field
LPW + 1
LPC + 1
HSYNC
PXCLK
PXDATA
ACBIAS
line 0
line 1
LSWC+1
LEWC+1
1
2
34
5
(LVTIME4.FEWC+1)/2
......
......
6
7
8
265
266
267
268
268
Even Field
......
VSYNC
(LVTIME2(odd) or 4(even).FSWC + 1)/2
(LVTIME3.FPW + 1)/2
......
......
......
Figure 14.13 NTSC interlace mode timing
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