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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
LCD CONTROLLER
Preliminary
14-12
VSYNC
HSYNC
(LVTIME1.FPW+1)/2
Odd Field
LPW + 1
LPC + 1
HSYNC
PXCLK
PD
ACBIAS
line 0
line 1
LSWC + 1
LEWC + 1
(LVTIME4.FEWC+1)/2
......
......
Even Field
......
VSYNC
......
(LVTIME2(odd) or 4(even).FSWC + 1)/2
......
......
(LVTIME3.FPW+1)/2
Figure 14.14 PAL interlace mode timing
Example
The frame memory has RGB565 type image source. The following code fragment
gives the major registers to be programmed for NTSC encoder interface.
HCLK = 72MHz, LCLK = 54MHz, PXCLK=27MHz
LCTRL = 0x041E8E03
LCTRL.YUV = 0 (RGB)
LCTRL.BPP = 0x4 (RGB565)
LCTRL.R2Y = 0x1
LCTRL.DP = 0x1
LCTRL.PXDW = 0x6 (16bits)
LCTRL.TV = 0x1
LCTRL.IAC = 0x0
LCTRL.IVS = 0x1
LCTRL.IHS = 0x1
LCTRL.IPX = 0x1
LCTRL.NI = 0x0
LCTRL.DEN = 0x1
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