TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
LCD CONTROLLER
Preliminary
14-16
IVS [11]
Inverted VSYNC signal
0
Normal
1
Inverted
IHS[10]
Inverted HSYNC signal
0
Normal
1
Inverted
IPX [9]
Inverted Pixel Clock
0
Data is driven onto the LCD’s data pins on the rising edge of pixel
clock pin
1
Data is driven onto the LCD’s data pins on the falling edge of pixel
clock pin
NI [7]
Non-interlace
0
Interface mode.
Odd field timing control: LVTIME1, LVTIME2
Even field timing control: LVTIME3, LVTIME4
1
Non-interlace mode
LVTIME1 and LVTIME3 must be same, and LVTIME2 and
LVTIME4 must be same.
TV[15]
TFT [4]
STN [3]
Description
0
0
1
Select STN-LCD mode
0
1
0
Select TFT-LCD mode
1
0
0
Select TV mode
In this mode, all values of LVTIMEn registers
are
divided
by
2.
Therefore,
if
LVTIME1.FPW is set to 5 HSYNC cycles,
LVTIME1.FPW is programmed to 9(= 5*2 –
1).
Other combinations are undefined and should not be used.
DEN [1]
Pixel Data Transfer Enable
0
Disable
If LEN is enabled, LCD controller only generates timing control
signals.
1
Enable
Normally, DEN must be always enabled to operate LCD controller and display pixel data
on LCD. Some LCD modules, however, have their own frame memory. In this case, if
the current frame is the same with previous frame, it needs not to be transferred to LCD
module for reducing power-consumption and bus-bandwidth.
LEN [0]
LCD controller Enable
0
Disable
1
Enable
LCD Clock Divider Register (LCLKDIV)
0x80000F04
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ACDIV
CLKDIV
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
