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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
LCD CONTROLLER
Preliminary
14-17
FIELD
Description
ACDIV [15:8]
AC Bias clock divisor(STN only).
The number of clock cycles to count between each toggle of
AC_BIAS pin.. ACBIAS is toggled every n HSYNC cycles if ACDIV
is {(lpw+1) *n – 1}.
CLKDIV [7:0]
Pixel clock divisor
Note that programming CLKDIV less than 3 is illegal for STN LCD.
PXCLK = LCLK / (2*CLKDIV)
(if CLKDIV = 0, PXCLK = LCLK)
LCD Horizontal Timing Register1 (LHTIME1)
0x80000F08
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
LPW
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
LPC
FIELD
Description
LPW [23:16]
Line Pulse Width is the number of pixel clock cycles.
LPC [10:0]
Line Pulse Count is the number of pixel clock cycles in each line minus
1 on the screen
TFT /NTSC(16bit)/PAL(16bit) : active horizontal pixels - 1
Color STN : (3 * Horizontal display size / pixel width) -1
Mono STN: (Horizontal display size / pixel width )- 1
LCD Horizontal Timing Register2 (LHTIME2)
0x80000F0C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
LSWC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
LEWC
FIELD
Description
LSWC [24:16]
Line Start Wait Cycle is the number of dummy pixel-clock cycles
minus 1 to insert from the start of each horizontal line of pixels.
LEWC [8:0]
Line End Wait Cycle is the number of dummy pixel-clock cycles minus
1 to insert before the end of each horizontal line of pixels.
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