TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
LCD CONTROLLER
Preliminary
14-21
LCD Status Register (LSTATUS)
0x80000F44
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
EF
DD
RU
FU
FIELD
Description
EF [3]
Even-Field(Read-Only)
0: odd field or frame
1: even field or frame
DD* [2]
Disable Done(Read/Clear).
If LEN is disabled, DD will be 1 after current frame has been
displayed.. As MDD of LIM register is cleared, it can be LCD interrupt
source
RU*[1]
Register Update(Read/Clear)
It indicates that all registers programmed are applied to current frame
data. As MRU of LIM register is cleared, it can be LCD interrupt
source.
FU*[0]
FIFO underrun(Read/Clear)
It indicates that FIFO underrun has been occurred. In this case, LCLK
frequency must be lower. As MFU of LIM register is cleared, it can be
LCD interrupt source.
For clearing a specified bit, it must be written to 1. If a interrupt is generated, LSTATUS
bits, which correspond to the interrupt sources, must be cleared. Otherwise, the uncleared
interrupt will be not generated any more.
LCD Interrupt Masking Registers (LIM)
0x80000F48
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
MDD MRU MFU
FIELD
Description
MDD[2]
Mask “Disable Done Interrupt”.
MRU[1]
Mask “Register Update Interrupt”.
MFU[0]
Mask “FIFO underrun(Read/Clear)”.
LCD Image Position(LIP)
0x80000F4C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Y[10:0]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X[10:0]
FIELD
Description
Y [10:0]
Y position to display
X [10:0]
X position to display
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
