TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
LCD CONTROLLER
Preliminary
14-9
14.5 TFT LCD
The LCDC supports 16bpp true-color non-palletized color displays for color TFT LCD.
Figure 14.9 show frame memory organization. If image source is YUV420 or YUV422,
YUV2RGB converer can be used as Y2R of LCTRL is set. And each YUV channel is
indicated by LIBA0, LIBA1, and LIBA2 register.
It generates the control signals for LCD driver such as, VSYNC, HSYNC, PXCLK,
PXDEN(ACBIAS) and PXDATA. Figure 14.10 shows PXDATA format in TFT mode.
The timing diagram of TFT mode is shown in Figure 14.12.
Figure 14.9 TFT LCD pixel data memory organization
*) intensity bit
Figure 14.10 TFT LCD output pixel data
The VSYNC and HSYNC frequency is controlled by the LPC and FLC field.
LPC = (Horizontal display size) – 1
FLC = (Vertical display size) – 1
And PXCLK frequency is determined by the CLKDIV value.
fPXCLK = fLCLK / (2 x CLKDIV)
(3)
The frequency of VSYNC signal is the frame rate. So the frame rate can be
calculated as follows:
fVSYNC = fPXCLK / [ (FSWC + FPW + FLC +FEWC)
x {(LSWC+1) + (LPC+1) + (LEWC+1) + (LPW+1)}]
Therefore, if FR is the required refresh rate in TFT mode, fPXCLK_REQ, which is the
required PXCLK, is the flowing.
fPXCLK_REQ = FR x {(LPW+1) + (LPC+1) + (LSWC+1) + (LEWC+1)}
x {(FSWC+1) + (FPW+1) + (FLC+1) +(FEWC+1)}
(4)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R[4:0]
G[5:0]
B[4:0]
PXDW
565
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R[4:0]
G[4:0]
B[4:0]
PXDW
555 I*
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I*
U4 or V4
U6 or V6
R1[4:0]
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
8BPP(U or V)
RGB565
RGB555
G1[5:0]
B1[4:0]
R1[4:0]
G1[4:0]
B1[4:0]
Y2
Y3
8BPP(Y)
I*
U0 or V0
U2 or V2
R0[4:0]
8BPP(U or V)
RGB565
RGB555
G0[5:0]
B0[4:0]
R0[4:0]
G0[4:0]
B0[4:0]
Y0
Y1
8BPP(Y)
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