TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
LCD CONTROLLER
Preliminary
14-5
31
p24
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
p25 p26 p27 p28 p29 p30 p31 p16 p17 p18 p19 p20 p21 p22 p23
p11
p10
p9
p8
p15
p14
p13
p12
p4
p5
p6
p7
p2
p3
p1
15
p8
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
p9 p10 p11 p12 p13 p14 p15 p0 p1 p2 p3 p4 p5 p6 p7
p0
p1
p2
p3
p7
p6
p5
p4
p0
p1
p2
p3
p0
p1
p0
2BPP
1BPP
4BPP
8BPP
16BPP
2BPP
1BPP
4BPP
8BPP
16BPP
b) BR=1
Figure 14.4 STN LCD pixel data organization
Figure 14.5 Color STN Pixel Data
ACBIAS signal is used by the LCD driver to alternate the polarity of the row and column
voltage used to turn the pixel on and off. It is controlled by the ACDIV field of
LCLKDIV register. This value must be (lpw+1) times.
ACDIV = {(lpw+1) * n} –1
n = number of HSYNC(CL1)
PXCLK frequency is determined by the CLKDIV field of LCLKDIV register as follows.
The minimum value of CLKDIV is 3 in STN mode.
fPXCLK
= fLCLK / (2 * CLKDIV)
(1)
VSYNC frequency is related to the field of FEWC, LSWC, LEWC, LPC, and FLC as
well as LCLK and PXCLK.
fVSYNC
= fPXCLK / [{(LPW+1) + (LPC+1) + (LSWC+1) + (LEWC+1)}
* {(FLC + 1) + (FPW+1)}]
Therefore, if FR is the required refresh rate, fPXCLK_REQ, which is the required PXCLK, is
the flowing.
fPXCLK_REQ = FR x [ {(LPW+1) + (LPC+1) + (LSWC+1) + (LEWC+1)}
* {(FLC + 1) + (FEWC+1)} ]
(2)
The LCDC contains dithering pattern registers for STN LCD: a 48-bit modulo 7 dithering
pattern register (LDP7L and LDP7H), a 32-bit modulo 5 dithering pattern register (LDP5),
a 16-bit modulo 4 dithering pattern register (LDP4), and a 16-bit modulo 3(LDP3)
dithering pattern register. These dithering pattern registers can contain the programmable
STN
8BPP
7
6
5
4
3
2
1
0
B[2:0]
G[2:0]
R[1:0]
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
B[3:0]
G[3:0]
R[3:0]
X
STN
16BPP
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
