TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
LCD CONTROLLER
Preliminary
14-6
pre-dithered pattern values for each duty cycle ratio. Bits per pixel of image determines
pre-dithered value.
If BPP is 4 or 16, pre-dithered value is non-palettized value, which is pixel data in the
frame memory. If BPP is 2, a nibble of LUTBL that is indexed by 2-bit pixel data is pre-
dithered value. If BPP is 8, each nibble of LUTRD, LUTGR, and LUTBL that is indexed
by pixel data, which consist of 3-bit R, 3-bit G, and 2-bit B, is pre-dithered value. Figure
14.6 shows the relationship between pre-dithered values and dithering pattern registers.
The LDP7H and LDP7L contain 5 pre-dithered patterns for 1/7, 3/7, 4/7, 5/7, and 6/7 duty
cycle rate. Each field of LDP7H and LDP7L is 7-bit long. The LDP5 has 4 pre-dithered
pattern fields for 1/5, 2/5, 3/5, and 4/5 duty cycle rate. Each field of LDP5 is 5-bit long.
The LDP4 has 3 pre-dithered pattern fields for 1/4, 1/2(=2/4), and 3/4 duty cycle rate, and
each field is 4-bit long. Likewise, the LDP3 has 2 fields for 1/3 and 2/3 duty cycle rate
with 3-bit length.
Note that the pre-dithered data for 1 and 0 is not defined in the dithering pattern register,
because these values are implemented with VDD and VSS condition.
Pre-dithered value
Dithering register
Duty cycle ratio
0
0
0
1
DP1_7
1/7
2
DP1_5
1/5
3
DP1_4
1/4
4
DP1_3
1/3
5
DP2_5
2/5
6
DP3_7
3/7
7
DP2_4
1/2
8
DP4_7
4/7
9
DP3_5
3/5
10
DP2_3
2/3
11
DP5_7
5/7
12
DP3_4
3/4
13
DP4_5
4/5
14
DP6_7
6/7
15
1
1
Figure 14.6 Dithering operation
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