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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
MEMORY CONTROLLER
Preliminary
15-2
Table 15.1 Memory Controller Register Map (Base Address = 0xF0000000)
Name
Address
Type
Reset
Description
SDCFG
0x00
R/W
0x62E97010
SDRAM Configuration Register
SDFSM
0x04
R
-
SDRAM FSM Status Register
MCFG
0x08
R/W
0xZZZZ_02
Miscellaneous Configuration Register
TST
0x0C
W
0x00000000
Test mode register
(must be remained zero)
CSCFG0
0x10
R/W
0x0B405649
Configuration Register for External Chip Select 0
(nCS0 pin)
CSCFG1
0x14
R/W
0x0150569A
Configuration Register for External Chip Select 1 (nCS1 pin)
CSCFG2
0x18
R/W
0x006056BA
Configuration Register for External Chip Select 2 (nCS2 pin)
CSCFG3
0x1C
R/W
0x0A70569A
Configuration Register for External Chip Select 3 (nCS3 pin)
CLKCFG
0x20
R/W
0xXXXXXX00
Memory Controller Clock Count Register
SDCMD
0x24
W
-
SDRAM Command Register
Table 15.2 NAND flash Register Map (Base Address = N * 0x10000000)
Name
Address
Type
Reset
Description
NDCMD
0x00
R/W
-
Command Cycle Register
NDLADR
0x04
W
-
LinearAddress Cycle Register
NDRADR
0x08
W
-
RowAddress Cycle Register
NDIADR
0x0C
W
-
SingleAddress Cycle Register
NDDATA
0x10
R/W
-
DataAccess Cycle Register
*) N represents BASE field of configuration register (CSCFGx ) for each chip select.
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