TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
MEMORY CONTROLLER
Preliminary
15-3
15.2 SDRAM Controller
The SDRAM controller supports from 16Mbit up to 512Mbit SDRAM.
The SDRAM parameter such as size, refresh period, RAS to CAS delay, refresh to idle delay can
be programmed by internal register. Refer to SDRAM cycle diagram in Figure 15.2
SDRAM Configuration Register (SDCFG)
0xF0000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CL
BW
CW
SDBASE
RC
RCD
RD[2:1]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RD[0]
RP
RW
Refresh
AM
APD
PPD
SR
*) The reset value means the following configuration.
CAS Latency = 2 cycles, CAS Width = 9bit, RAS Width = 12bit,
Bus Width = 16bit, SDBASE = 0x20000000
tRC = 7 cycles, tRCD = 2 cycles, tRD = 2 cycles, tRP = 7 cycles, Refresh = (512 + 15) cycles
Except for Bit 0 (SR), the sequence below must be followed whenever this register is written.
1.
Clear SDEN bit of MCFG register (SDRAM controller is disabled)
2.
Update SDCFG register value
3.
Set SDEN bit of MCFG register (SDRAM controller is enabled and MRS cycle is
issued to the SDRAM).
Although the reset value of SDEN bit is “0”, the boot ROM enables the SDEN bit in JTAG debug mode,.
Thus, do not rely on the default value of SDEN bit. Always follow the sequence above if JTAG debugging
is required.
CL [31]
CAS Latency (tCL)
0
CAS latency is 2 cycle
1
CAS latency is 3 cycle
*) Do not change this bit when SDEN bit of MCFG register is “1”. Disable SDEN first. After this bit is
written, SDEN bit must be re-enabled for SDRAM MRS cycle.
BW [30]
Bus Width Select
0
Bus width for SDRAM is 32 bit (valid only in TCC761)
1
Bus width for SDRAM is 16 bit
CW [29:28]
CAS Width
0, 1
8 bit is used for CAS address
2
9 bit is used for CAS address
3
10 bit is used for CAS address
*) 16Mbit : CAS = 8 bit, RAS = 11 bit
64Mbit : CAS = 8 bit, RAS = 12 bit
128Mbit : CAS = 9 bit, RAS = 12 bit
256Mbit : CAS = 9 bit, RAS = 13 bit
512Mbit : CAS =10bit, RAS = 13 bit
SDBASE
[27:24]
SDRAM Base Address
N
Indicates the MSB 4bit of SDRAM area. That is SDRAM base =
0xN0000000
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