TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
MEMORY CONTROLLER
Preliminary
15-4
RC [23:21]
Delay of Refresh to Idle (tRC)
n
n number of HCLK cycle is used to meet the refresh to idle delay time
RCD [20:18]
Delay of RAS to CAS (tRCD)
n
(n+1) number of HCLK cycle is used to meet the RAS to CAS delay time
RD [17:15]
Delay of Read to Precharge (tRD)
n
n number of HCLK cycle is used to meet the read to precharge time
RP [14:12]
Delay of Precharge to Refresh (tRP)
n
(n+1) number of HCLK cycle is used to meet the precharge to refresh time
RW [11:10]
RAS Width
{x,1}
11bit is used for RAS address bus
{0,0}
12bit is used for RAS address bus
{1,0}
13bit is used for RAS address bus
*) 16Mbit : CAS = 8 bit, RAS = 11 bit
64Mbit : CAS = 8 bit, RAS = 12 bit
128Mbit : CAS = 9 bit, RAS = 12 bit
256Mbit : CAS = 9 bit, RAS = 13 bit
512Mbit : CAS =10bit, RAS = 13 bit
Refresh [9:4]
Refresh Cycle
n
Every (n * 512 + 15) number of HCLK cycle has passed, the SDRAM
refresh request is generated. If on going cycle has finished, the refresh
cycle starts. Real refresh period depends on the period of HCLK.
AM
Address Matching Configuration Bit
0
BA-RAS-CAS
1
RAS-BA-CAS
APD
Reserved
0
Reserved for ChipTest. Must be written as “0”
PPD
Precharge Power-Down Mode
0
Disable precharge power-down mode
1
Enable precharge power-down mode
When sdram in precharge-idle state, CKE signal would be zero for power-
down. In this case, the redundant 1 cycle is needed to enter the active state.
SR
Self-Refresh Mode
0
Exit from the self-refresh mode
1
Enter the self-refresh mode
SDRAM FSM Status Register (SDFSM)
0xF0000004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
SDFSM
This register is read only and represents current status of finite state machine in the SDRAM
controller. This can be used for test purpose only.
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