TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
MEMORY CONTROLLER
Preliminary
15-6
15.3 Miscellaneous Configuration
In this register, there are various special flags for the TCC76x system.
One of them is for supporting boot PROM. At initialization, the lower address space
(0x00000000 ~ 0x0FFFFFFF) is mapped to internal or external boot ROM. But after
initialization, these space must be mapped to a RAM as the system program including interrupt
vector table is located in this area. To satisfy this requirement, the TCC76x provide RM(Remap)
flag.
BM flag is used to select one of the boot procedures. Refer to Section “BOOTING
PROCEDURE” for details. BM flag contains the state of GPIO_B[24,22,21] pins at the rising
edge of the nRESET pin.
BW flag is used to detect the initial system bus width configuration. This flag is read-only, and
contains the state of GPIO_A[9:8] pin at the rising edge of nRESET pin. So user can control the
bus width by pulling up or down the GPIO_A[9:8] pin.
Miscellaneous Configuration Register (MCFG)
0xF0000008
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
XXXX
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RDY XDM
X
BW
BM
SDW
SDT
JTEN SDEN SDS
SRF
GPO
RM
RDY [15]
Type
Bus Ready Flag
0
Represent that READY pin is low.
1
R
Represent that READYpin is high.
*) This flag reflects READY pin’s state. READY pin is used to extend the access cycle for the
external memories. It can control directly the cycle of external memory access by setting the
URDY bit of each configuration register and also can be used as a ready flag by polling the state
of this bit, especially for NAND flash interfacing.
XDM [14]
Type
Data-Bus Output Mode
0
In idle state, the data bus would be in input-mode. (Default)
1
R/W
In idle state, the data bus would be in output mode.
BW [12:11]
Type
Bus Width Flag
00, 01
The corresponding memory is configured by 32bit data
bus. The 32bit bus width is valid only in TCC761.
10
The corresponding memory is configured by 16bit data bus.
11
R
The corresponding memory is configured by 8bit data bus.
BW is the status of GPIO_A[9:8] at the rising edge of nRESET signal. The bus-width of
memory attached at nCSx register is determined as follows.
BW (of CSCFGx) = BW (of MCFG) ^ BW (that user want)
BM [10:8]
Type
Boot Mode
n
R
The state of GPIO_B[24,22,21] pins at reset. Refer to Chapter
“BOOTING PROCEDURE” for boot mode.
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