TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
MEMORY CONTROLLER
Preliminary
15-9
15.4 External Memory Controller
External memory controller can control external memories such as NAND or NOR type flash
memory and ROM, SRAM type memory. These memories are selected by nCS3 ~ nCS0 pins.
The cycle parameter for accessing external memory can be configured by internal registers. In
case of NAND flash, additional parameters for address, command and data cycles can be
provided.
External Chip Select n Configuration Register (CSCFGx)
0xF0000010 + (x * 4)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
OD
WD
PW[7:6]
BW
MTYPE
CSBASE
URDY
RDY
PW[5:4]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PW[3] AMSK
PSIZE
CADR
STP
PW[2:0]
HLD
*) The reset value of each CSCFGx register means the following configuration for each chip select.
Chip Select 0 : 16bit, SRAM, Base = 0x40000000, tSTP=1, tPW=2, tHLD=1
Chip Select 1 : 32bit,
IDE, Base = 0x50000000, not use Ready, tSTP=2, tPW=4, tHLD=2
Chip Select 2 : 32bit, NAND, Base = 0x60000000,AMSK=1, PSIZE=1, CADR=3, tSTP=2, tPW=8, tHLD=2
Chip Select 3 : 16bit, NOR, Base = 0x70000000, tSTP=2, tPW=4, tHLD=2
OD
Delayed ‘OE’ Signal
0
Normal STP and HLD timing would be applied.
1
When STP and HLD are zero, 1 cycle would be added for delayed by
half-pulse for OE signal
WD
Delayed ‘WE’ Signal
0
Normal STP and HLD timing would be applied.
1
When STP and HLD are zero, 1 cycle would be added for delayed by
half-pulse for WE signal
*bw [27:26]
Bus Width Select
0, 1
Bus width = 32 bit (valid only in TCC761)
2
Bus width = 16 bit
3
Bus width = 8 bit
*) bw is calculated by xoring the BW field of MCFG register and BW field of CSCFGx register,
that is bw = BW(of MCFG) ^ BW(of CSCFGx). BW(of MCFG) is acquired by the status of
GPIO_A[9:8] at the rising edge of nRESET signal. So, if user want to set bus-width
independently to the BW of MCFG, you must set the BW of CSCFGx as like as the follows.
BW (of CSCFGx) = BW (of MCFG) ^ BW (that user want)
MTYPE [25:24]
Type of External Memory
0
NAND type
1
IDE type
2
SMEM_0 type (Ex : ROM, NOR flash)
Byte write control signal (DQM) is not needed.
3
SMEM_1 type (Ex : SRAM)
Byte write control signal (DQM) is needed.
CSBASE [23:20]
Chip Select n Base Address
M
Indicates the MSB 4bit of nCS[n] area.
The base address of nCS[n] is set to M * 0x10000000.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
