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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
MEMORY CONTROLLER
Preliminary
15-11
XA
nWE
nCS
tSH
ADDR0
DQ
DQ
R
SMEM_0 Type Cycle (Bus width >= Data width, URDY=0)
ADDR1
nOE
DQ
W
tHLD
tPW
tSH
tHLD
tPW
SMEM_0 Type Cycle (Bus width < Data width, URDY=1, RDY=0)
XA
nCS
tSH
ADDR0
DQ
DQ
RL
ADDR1
nOE
tHLD
tPW
2
tPW
DQ
RH
nWE
tSH
ADDR0
SMEM_1 Type Cycle (Bus width >= Data width, URDY=0)
ADDR1
nOE
DQ
1
tHLD
tPW
tSH
tHLD
tPW
nCS
XA
DQM1
DQM0
DQ[15:8]
DQ[7:0]
DQ
0
READY
tPW
1
tWait
tWait
tSH1
tSH2
tPW + tWait =
tPW
1 + tPW2 + tWait
tSH + tWait =
tSH
1 + tSH2 + tWait
tHLD
Figure 15.3 Basic Timing Diagram for External Memories
In case of IDE type memories, there are two chip-enable signals for it. In the TCC76x, each
enable signal can be controlled by offset address space. ‘nCS0’ reflects that the offset address
range of 0 ~ 0x1F is accessed, ‘nCS1’ reflects that 0x20 ~ 0x3F is accessed. For larger address
than 0x3F, if bit5 of address value means which enable signal is activated. (0 to ‘nCS0’, 1 to
‘nCS1’)
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