TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
MEMORY CONTROLLER
Preliminary
15-7
SDW [7]
Type
SDRAM High-Frequency Wait
0
No additive wait cycle
1
R/W
Additive wait cycle
SDT [6]
Type
Type of SDRAM
0
Single-Data-Rate SDRAM
1
R/W
Double-Data-Rate SDRAM
JTEN [5]
Type
JTAG Enable
0
JTAG port is disabled
1
R/W
JTAG port is enabled
SDEN [4]
Type
SDRAM Controller Enable
0
SDRAM controller is disabled
1
R/W
SDRAM controller is enabled
*) When this bit goes from low to high, SDRAM MRS cycle is generated.
This bit must be cleared before CL bit of SDCFG register is changed.
SDS [3]
Type
SD_CLK output select
0
SDRAM Clock is out from SD_CLK pin
1
R/W
GPO bit is out from SD_CLK pin
SRF [2]
Type
Self Refresh Cycle Generation
0
If SDRAM is in standby mode, the refresh cycle is generated a
few times automatically, and SDRAM exits from standby state
and goes back into idle state.
1
R/W
If SDRAM is not in standby mode, the self-refresh cycle is
generated, and the SDRAM enters into standby mode and stay
this mode until this flag goes back to low.
*) Do not set while program is executing in SDRAM. SR bit of SDCFG register has the same
function.. Either one can be used for self-refresh mode control.
It is recommended to use the following example sequence to control self-refresh mode.
To enable self-refresh mode,
1.
Manipulate cache coherency if necessary.
2.
Set SR bit of SDCFG register
3.
Set SDS bit of MCFG register
To exit from self-refresh mode,
1.
Clear SDS bit of MCFG register
2.
Clear SR bit of SDCFG register
The above sequences must be executed in the non-SDRAM area, like internal SRAM or NOR
flash and while the SDRAM is in self-refresh mode, code should not access the SDRAM area.
GPO [1]
Type
SD_CLK output
0 / 1
R/W
When SDS bit is high, this bit is out through SD_CLK pin
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