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TPS25751AS Datasheet(PDF) 14 Page - Texas Instruments |
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TPS25751AS Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 85 page  6.10 PP_EXT Characteristics - TPS25751AS (continued) Operating under these conditions unless otherwise noted: , 3V ≤ VLDO_3V3 ≤ 3.6V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VGATE_ON Sourcing voltage (ON) 0V ≤ VVSYS ≤ 22V, IGATE_VSYS < 4µA, measure VGATE_VSYS – VVSYS, VVBUS > 4V 6 12 V 4V ≤ VVBUS ≤ 22V, IGATE_VBUS < 4µA, measure VGATE_VBUS – VVBUS 6 12 V VRCP Comparator mode RCP threshold, VVSYS - VVBUS 4V ≤ VVBUS ≤ 22V, VVIN_3V3 ≤ 3.63V 2 6 10 mV IGATE_OFF Sinking strength Normal turnoff: VVSYS = 5V, VGATE_VSYS = 6V, measure IGATE_VSYS 13 µA Normal turnoff: VVBUS = VVSYS = 5V, VGATE_VBUS = 6V, measure IGATE_VBUS 13 µA RGATE_FSD Sinking strength Fast turnoff: VVSYS = 5V, VGATE_VSYS = 6V, assert PPHV1_FAST_DISABLE, measure RGATE_VSYS 85 Ω Fast turnoff: VVBUS = VVSYS = 5V, VGATE_VBUS = 6V, assert PPHV1_FAST_DISABLE, measure RGATE_VBUS 85 Ω RGATE_OFF_UVLO Sinking strength in UVLO (safety) VVIN_3V3 = 0V, VVBUS = 3V, VGATE_VSYS = 0.1V, measure resistance from GATE_VSYS to GND 1.5 MΩ SS Soft start slew rate for GATE_VSYS 4V ≤ VVBUS ≤ 22V, ILOAD = 100mA, 500pF < CGATE_VSYS < 16nF, measure slope from 10% to 90% of final VSYS value 2.8 3.3 3.80 V/ms tGATE_VBUS_OFF Time allowed to disable the external FET via GATE_VBUS in normal shutdown mode.(1) VVBUS = 20V, QG of external FET = 40nC or CGATE_VBUS < 3nF, gate is off when VGATE_VBUS – VVBUS < 1V 450 4000 µs tGATE_VBUS_OVP Time allowed to disable the external FET via GATE_VBUS in fast shutdown mode (VOVP4RCP exceeded), this includes the response time of the comparator(1) OVP: VOVP4RCP = setting 57, VVBUS = 20V initially, then raised to 23V in 50ns, QG of external FET = 40nC or CGATE_VBUS < 3nF, gate is off when VGATE_VBUS – VVBUS < 1V 3 5 µs tGATE_VBUS_RCP Time allowed to disable the external FET via GATE_VBUS in fast shutdown mode (VRCP exceeded), this includes the response time of the comparator(1) RCP: VRCP = setting 0, VVBUS = 5V, VVSYS = 5V initially, then raised to 5.5V in 50ns, QG of external FET = 40 nC or CGATE_VBUS < 3nF, gate is off when VGATE_VBUS – VVBUS < 1V 1 2 µs tGATE_VSYS_OFF Time allowed to disable the external FET via GATE_VSYS in normal shutdown mode(1) VVSYS= 20V, QG of external FET = 40nC or CGATE_VBUS < 3nF, gate is off when VGATE_VSYS – VVSYS < 1V 450 4000 µs TPS25751A SLVSJG7 – MAY 2026 www.ti.com 14 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: TPS25751A |
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