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TPS25751AS Datasheet(PDF) 20 Page - Texas Instruments |
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TPS25751AS Datasheet(HTML) 20 Page - Texas Instruments |
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20 / 85 page  6.18 BC1.2 Characteristics (continued) Operating under these conditions unless otherwise noted: 3V ≤ VLDO_3V3 ≤ 3.6V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RDCP_DAT Dedicated Charging Port Resistance 0.5V ≤ VUSB_P ≤ 0.7V, 25µA ≤ IUSB_N ≤ 175µA 200 Ω 6.19 I2C Requirements and Characteristics Operating under these conditions unless otherwise noted: 3V ≤ VLDO_3V3 ≤ 3.6V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I2Ct_IRQ OD_VOL_IRQ Low level output voltage IOL = 2mA 0.4 V OD_LKG_IRQ Leakage Current Output is Hi-Z, VI2Cx_IRQ = 3.45V –1 1 µA I2Cc_IRQ IRQ_VIH High-Level input voltage VLDO_3V3 = 3.3V 1.3 V IRQ_VIH_THRESH High-Level input voltage threshold VLDO_3V3 = 3.3V 0.72 1.3 V IRQ_VIL low-level input voltage VLDO_3V3 = 3.3V 0.54 V IRQ_VIL_THRESH low-level input voltage threshold VLDO_3V3 = 3.3V 0.54 1.08 V IRQ_HYS input hysteresis voltage VLDO_3V3 = 3.3V 0.09 V IRQ_DEG input deglitch 20 ns IRQ_ILKG I2Cc_IRQ leakage current VI2Cc_IRQ = 3.45V –1 1 µA SDA and SCL Common Characteristics (Common Characteristics) VIL Input low signal VLDO_3V3 = 3.3V 0.54 V VIH Input high signal VLDO_3V3 = 3.3V 1.3 V VHYS Input hysteresis VLDO_3V3 = 3.3V 0.165 V VOL Output low voltage IOL = 3mA 0.36 V ILEAK Input leakage current Voltage on pin = VLDO_3V3 –3 3 µA IOL Max output low current VOL = 0.4V 15 mA IOL Max output low current VOL = 0.6V 20 mA tf Fall time from 0.7 × VDD to 0.3 × VDD VDD = 1.8V, 10pF ≤ Cb ≤ 400pF 12 80 ns VDD = 3.3V, 10pF ≤ Cb ≤ 400pF 12 150 ns tSP I2C pulse width suppressed 50 ns CI Pin capacitance (internal) 10 pF Cb Capacitive load for each bus line (external) 400 pF SDA and SCL Standard Mode Characteristics (Target) fSCLS Clock frequency for target VDD = 1.8V or 3.3V 100 kHz tVD;DAT Valid data time Transmitting Data, VDD = 1.8V or 3.3V, SCL low to SDA output valid 3.45 µs tVD;ACK Valid data time of ACK condition Transmitting Data, VDD = 1.8V or 3.3V, ACK signal from SCL low to SDA (out) low 3.45 µs SDA and SCL Fast Mode Characteristics (Target) fSCLS Clock frequency for target VDD = 1.8V or 3.3V 100 400 kHz tVD;DAT Valid data time Transmitting data, VDD = 1.8V, SCL low to SDA output valid 0.9 µs TPS25751A SLVSJG7 – MAY 2026 www.ti.com 20 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: TPS25751A |
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