TPS25751AS datasheet(76/85 Pages) TI2

76 / 85 page

When routing the VBUS power plane from the Type-C connector to the TPS25751AS VBUS pins, minimize

bottle necks caused by other vias and traces to improve current flow. The example layout shown in Figure 9-28to

route the VBUS plane from the connector to TPS25751AS.

9.4.2.2.2.5 TPS25751AS I/O

I2C, ADCIN1/2, and GPIO pins

Fan these traces out from the TPS25751AS, use vias to connect the net to a routing layer if needed. For these

nets, use 4mil to 10mil trace width.

I2Cc_SDA/SCL/IRQ (pins 8, 9, and 10) and I2Ct_SCL/SDA/IRQ (pins 15, 16, and 17)

Minimize trace width changes to avoid I2C communication issues.

ADCIN1 and ADCIN2 (pins 2 and 3)

Keep the ADCINx traces away from switching elements. If a resistor divider is used, place the divider close to

LDO_3V3 or LDO_1V5.

GPIO (pins 5, 6, 7, 13, 18, 22, 23, 30, and 31)

Separate GPIO traces running in parallel by a trace width. Keep the GPIOx traces away from switching

elements.

9.4.2.2.2.6 TPS25751AS PPEXT Gate Driver

GATE_VSYS (pin 20)

The GATE_VSYS pin (pin 20) can be connected with a trace (recommended 6mil trace width) to the gate pins of

the N-ch MOSFET with source tied to PPHV. It is recommended to NOT via directly to the gate pin of the N-ch

MOSFET, instead use via(s) to connect the GATE_VSYS pin from the TPS25751AS to the gate pin of the N-ch

MOSFET. Refer to Figure 9-25 and Figure 9-26 for examples on how to connect the traces.

GATE_VBUS (pin 21)

The GATE_VBUS pin (pin 21) can be connected with a trace (recommended 6mil trace width) to the gate pins of

the N-ch MOSFET with source tied to VBUS. It is recommended to NOT via directly to the gate pin of the N-ch

MOSFET, instead use via(s) to connect the GATE_VBUS pin from the TPS25751AS to the gate pin of the N-ch

MOSFET. Refer to Figure 9-25 and Figure 9-26 for examples on how to connect the traces.

9.4.2.2.2.7 TPS25751AS GND

The GND pad is used to dissipate heat for the TPS25751AS device. Connect the GND pins (11, 12, and 14) to

the Ground pad underneath the TPS25751AS device. Connect the through hole vias from the ground pad on the

top layer to a copper pour on the bottom layer to help dissipate heat. Additional vias can be added to improve

thermal dissipation.

TPS25751A

SLVSJG7 – MAY 2026

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TPS25751AS Datasheet(PDF) 76 Page - Texas Instruments