TPS25751AS datasheet(62/85 Pages) TI2

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9.3 Power Supply Recommendations

9.3.1 3.3V Power

9.3.1.1 VIN_3V3 Input Switch

The VIN_3V3 input is the main supply of the TPS25751A device. The VIN_3V3 switch (see Section 8.3.2)

is a uni-directional switch from VIN_3V3 to LDO_3V3, not allowing current to flow backwards from LDO_3V3

to VIN_3V3. This switch is on when the 3.3V supply is available and the dead battery flag is cleared. The

recommended capacitance CVIN_3V3 (see Section 6.4) must be connected from the VIN_3V3 pin to the GND pin.

Do not power VIN_3V3 from VBUS.

9.3.2 1.5V Power

The internal circuitry is powered from 1.5V. The 1.5V LDO steps the voltage down from LDO_3V3 to 1.5V. The

1.5V LDO provides power to all internal low-voltage digital circuits which includes the digital core and memory.

The 1.5V LDO also provides power to all internal low-voltage analog circuits. Connect the recommended

capacitance CLDO_1V5 (see Section 6.4) from the LDO_1V5 pin to the GND pin.

9.3.3 Recommended Supply Load Capacitance

Section 6.4 lists the recommended board capacitances for the various supplies. The typical capacitance is the

nominally rated capacitance that must be placed on the board as close to the pin as possible. The maximum

capacitance must not be exceeded on pins for which it is specified. The minimum capacitance is minimum

capacitance allowed for tolerances and voltage derating ensuring proper operation.

9.4 Layout

9.4.1 TPS25751AD - Layout

9.4.1.1 Layout Guidelines

Proper routing and placement maintain signal integrity for high speed signals and improve the heat dissipation

from the power paths. The combination of power and high speed data signals are easily routed if the following

guidelines are followed. Best practice is to consult with board manufacturing to verify manufacturing capabilities.

9.4.1.1.1 Recommended Via Size

Proper via stitching is recommended to carrying current for the VBUS power paths and grounding. The

recommended minimum via size is shown below, but larger vias are an option for low density PCB designs.

A single via is capable of carrying 1A, verify the tolerance with the board manufacturing. Vias are recommended

to be tented when located close to the PD controller.

16mil

8mil

Figure 9-15. Recommend Minimum Via Size

9.4.1.1.2 Minimum Trace Widths

Below are the minimum trace widths for analog and digital pins. The trace width limitations are also defined by

the board manufacturing process used. Consult with manufacturing for determining the minimum trace widths

and tolerance.

TPS25751A

SLVSJG7 – MAY 2026

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TPS25751AS Datasheet(PDF) 62 Page - Texas Instruments