TPS25751AS datasheet(69/85 Pages) TI2

69 / 85 page

Fan these traces out from the TPS25751AD, use vias to connect the net to a routing layer if needed. For these

nets, use 4mil to 10mil trace width.

I2Cc_SDA/SCL/IRQ (pins 8, 9, and 10) and I2Ct_SCL/SDA/IRQ (pins 16, 17, and 18)

Minimize trace width changes to avoid I2C communication issues.

ADCIN1 and ADCIN2 (pins 2 and 3)

Keep the ADCINx traces away from switching elements. If a resistor divider is used, place the divider close to

LDO_3V3 or LDO_1V5.

GPIO (pins 5, 6, 7, 19, 26, 27, 37, 36, and 13)

Separate GPIO traces running in parallel by a trace width. Keep the GPIOx traces away from switching

elements.

9.4.1.2.2.6 TPS25751AD DRAIN

The DRAIN pad is used to dissipate heat for the internal high voltage power path (PPHV). Connect the Drain

pins (pins 15 and 30) to the Drain pad underneath the TPS25751AD device. Connect the through hole vias from

the drain pad on the top layer to a copper pour on the bottom layer to help dissipate heat. Additional vias can be

added to improve thermal dissipation.

9.4.1.2.2.7 TPS25751AD GND

The GND pad is used to dissipate heat for the TPS25751AD device. Connect the GND pins (pins 11, 12, 14 and

31) to the Ground pad underneath the TPS25751AD device. Connect the through hole vias from the ground pad

on the top layer to a copper pour on the bottom layer to help dissipate heat. Additional vias can be added to

improve thermal dissipation.

9.4.2 TPS25751AS - Layout

9.4.2.1 Layout Guidelines

Proper routing and placement maintain signal integrity for high speed signals and improve the heat dissipation

from the power paths. The combination of power and high speed data signals are easily routed if the following

guidelines are followed. Best practice is to consult with board manufacturing to verify manufacturing capabilities.

9.4.2.1.1 Recommended Via Size

Proper via stitching is recommended to carrying current for the VBUS power paths and grounding. The

recommended minimum via size is shown below, but larger vias are an option for low density PCB designs.

A single via is capable of carrying 1A, verify the tolerance with the board manufacturing. Vias are recommended

to be tented when located close to the PD controller.

16mil

8mil

Figure 9-23. Recommend Minimum Via Size

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TPS25751A

SLVSJG7 – MAY 2026

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TPS25751AS Datasheet(PDF) 69 Page - Texas Instruments