TPS25751AS datasheet(47/85 Pages) TI2

47 / 85 page

The controller must wait until the clock line transitions high plus an additional minimum time (4μs for standard

100kbps I2C) before pulling the clock low again.

Any clock pulse can be stretched and typically the clock pulse before or after the acknowledgment bit is

stretched.

8.3.10.2.1.2 I2C Address Setting

The I2C controller must only use I2Ct_SCL/SDA for loading a patch bundle.

Once the boot process is complete, the port has a unique target address on the I2Ct_SCL/SDA bus as selected

by the ADCINx pins.

Table 8-5. I2C Default Target Address for I2Ct_SCL/SDA.

I2C ADDRESS INDEX

(DECODED FROM ADCIN1

AND ADCIN2)(1)

TARGET ADDRESS

AVAILABLE

DURING BOOT

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

R/W

Yes

R/W

Yes

R/W

Yes

R/W

Yes

(1)

See Pin Strapping to Configure Default Behavior details about ADCIN1 and ADCIN2 decoding.

8.3.10.2.1.3 Unique Address Interface

The Unique Address Interface allows for complex interaction between an I2C controller and a single TPS25751A.

The I2C target sub-address is used to receive or respond to Host Interface protocol commands. Figure 8-29 and

Figure 8-30 show the write and read protocol for the I2C target interface, and a key is included in Figure 8-31

to explain the terminology used. The key to the protocol diagrams is in the SMBus Specification and is repeated

here in part.

Unique Address

Byte Count = N

Data Byte 1

Data Byte 2

Data Byte N

Figure 8-29. I2C Unique Address Write Register Protocol

Unique Address

Byte Count = N

Unique Address

Data Byte N

Data Byte 1

Data Byte 2

Figure 8-30. I2C Unique Address Read Register Protocol

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TPS25751A

SLVSJG7 – MAY 2026

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