TPS25751AS datasheet(45/88 Pages) TI2

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8.3.10.2 I2C Interface

The TPS25751A features two I2C interfaces that use an I2C I/O driver like the one shown in Figure 8-25. This I/O

consists of an open-drain output and an input comparator with de-glitching.

I2C_SDA/SCL

I2C_DO

I2C_DI

50ns

Deglitch

Figure 8-25. I2C Buffer

The TPS25751A has one I2C target interface ports: I2Ct. I2C port I2Ct is comprised of the I2Ct_SDA, I2Ct_SCL,

and I2Ct_IRQ pins. This interface provide general status information about the TPS25751A, as well as the

ability to control the TPS25751A behavior, supporting communications to/from a connected device and/or cable

supporting BMC USB-PD, and providing information about connections detected at the USB-C receptacle.

When the TPS25751A is in 'APP' mode TI recommends to use standard mode or Fast mode (that is a clock

speed no higher than 400kHz). However, in the BOOT mode when a patch bundle is loaded Fast Mode Plus can

be used (see fSCLS).

The TPS25751A has one I2C controller interface port. I2C is comprised of the I2Cc_SDA, I2Cc_SCL, and

I2Cc_IRQ pins. This interface can be used to read from or write to external target devices.

During boot, the TPS25751A attempts to read patch and Application Configuration data from an external

EEPROM with a 7-bit target address of 0x50. The EEPROM must be at least 32 kilo-bytes.

Table 8-4. I2C Summary

I2C BUS

TYPE

TYPICAL USAGE

I2Ct

Target

Optionally can be connected to an external MCU. Also used to load the patch and application

configuration.

I2Cc

Controller

Connect to a I2C EEPROM, Battery Charger. Use the LDO_3V3 pin as the pullup voltage. Multi-

controller configuration is not supported.

8.3.10.2.1 I2C Interface Description

The TPS25751A supports Standard and Fast mode I2C interfaces. The bidirectional I2C bus consists of the

serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pullup

resistor. Data transfer can be initiated only when the bus is not busy.

A controller sending a Start condition, a high-to-low transition on the SDA input and output, while the SCL input

is high initiates I2C communication. After the Start condition, the device address byte is sent, most significant bit

(MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA

input/output during the high of the ACK-related clock pulse. On the I2C bus, only one data bit is transferred

during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period

as changes in the data line at this time are interpreted as control commands (Start or Stop). The controller sends

a Stop condition, a low-to-high transition on the SDA input and output while the SCL input is high.

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TPS25751A

SLVSJG7 – MAY 2026

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