TPS25751AS datasheet(75/88 Pages) TI2

75 / 88 page

9.4.2.2.2.1 TPS25751AS Component Placement

LDO_1V5 (pin 4), LDO_3V3 (pin 1), and VIN_3V3 (pin 32)

The decoupling capacitors for LDO_3V3, LDO_1V5, and VIN_3V3 (C15, C16, and C17 respectively) need to

be placed as close as possible to TPS25751AS device for optimal performance. To minimize solution size, the

decoupling capacitors are placed on the bottom layer with their ground pads directly underneath the ground pad

of TPS25751AS. Use a maximum of one via per pin from TPS25751AS to the decoupling capacitors if placed

on a different layer. Use a minimum of 10mil trace width to route these three traces, preferably with 16mil trace

width if possible.

CC1 (pin 24) and CC2 (pin 25)

CC1 (C11) and CC2 (C10) capacitors need to be placed as close as possible to their respective pins and on the

same layer as the TPS25751AS device. When routing the CCx traces, DO NOT via to another layer in between

the CCx pins of the TPS25751AS to the CCx capacitors. Check to make sure the CCx capacitors are not placed

outside the CC trace creating an antenna, instead have the traces pass directly through the CCx capacitor pads

as shown in the example layout (refer to Figure 9-25). Use a minimum of 10mil trace width to enable Vconn

support (5V/0.6A).

9.4.2.2.2.2 TPS25751AS PP5V

The 10uF decoupling capacitor (C8) need to be placed as close as possible to the PP5V pins of TPS25751AS.

DO NOT use traces for PP5V. The PP5V power plane needs to be sized to support up to 3.6A (up to 3A

for sourcing, 600mA for Vconn). When connecting the PP5V pins (pins 28 and 29) to the 5V power plane,

use a minimum of 4 vias in parallel and close to the device to improve current sharing. Minimize the bottle

necks caused by other vias or traces, large bottle necks reduce the efficiency of the power plane. The bulk

capacitors (C6, C7, and C9) represent capacitances from the system 5V rail, these are placed further away from

TPS25751AS on the same PP5V power plane. Refer to Figure 9-25 and Figure 9-26 for placement and trace

reference.

9.4.2.2.2.3 TPS25751AS PP_EXT

Place the PP_EXT decoupling capacitors (C12, C13, and C14) as close as possible to TPS25751AS. These

capacitors do not need to be on the same layer as the device. The PP_EXT power plane needs to be sized to

support up to 5A of current. When connecting the PP_EXT plane to a different layer, use a minimum of 6 vias

in parallel per layer change. It is highly recommended to have more than 6 vias if possible for layer change to

improve current sharing and efficiency.

VSYS (pin 19)

The VSYS pin (pin 19) can be connected with a trace (recommended 6mil trace width) to any of the vias on the

PPHV plane. It is recommended to connect to a via close to the source pin of the VSYS N-ch MOSFET(pins A2,

B2, D2, and E2 of the Q1 FET in the example schematic) to improve reverse current sensing protection. Refer to

the Detailed Description for RCP for additional information on RCP.

9.4.2.2.2.4 TPS25751AS VBUS

VBUS (pins 26 and 27)

Place the VBUS decoupling capacitor (C1) as close as possible to TPS25751AS, the capacitor does not need

to be on the same layer as the device. The VBUS power plane need to be sized to support up to 5A of current

if 100W application is required. When connecting the VBUS pins (pins 26 and 27) plane to a different layer,

use a minimum of 3 vias per layer change. When connecting the VBUS power plane to a different layer, use a

minimum of 6 vias per layer change. Refer to Figure 9-25 and Figure 9-26 for capacitors and via placement.

At the Type-C port/connector, it is recommended to use minimum of 6 vias from the connector VBUS pins for

layer changes. Place the 10nF caps (C2, C3, C4, and C5) and the 22V TVS diode (U2) as close as possible to

the connector VBUS pins as shown inFigure 9-26.

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TPS25751A

SLVSJG7 – MAY 2026

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