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TPS25751AS Datasheet(PDF) 46 Page - Texas Instruments

Part # TPS25751AS
Description  TPS25751A USB Type-C® and USB PD Controller With Integrated Power Switches Optimized for DRP Power Applications
PDF  88 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TPS25751AS Datasheet(HTML) 46 Page - Texas Instruments

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Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a
target receiver is addressed, it must generate an ACK after each byte is received. Similarly, the controller must
generate an ACK after each byte that it receives from the target transmitter. Setup and hold times must be met
for proper operation.
A controller receiver signals an end of data to the target transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the target by holding the SDA line high. In this event, the transmitter
must release the data line to enable the controller to generate a Stop condition.
Figure 8-26 shows the start and stop conditions of the transfer. Figure 8-27 shows the SDA and SCL signals for
transferring a bit. Figure 8-28 shows a data transfer sequence with the ACK or NACK at the last clock pulse.
P
S
Start Condition
Stop Condition
SDA
SCL
Figure 8-26. I2C Definition of Start and Stop Conditions
Data Line
Change
SDA
SCL
Figure 8-27. I2C Bit Transfer
SCL from
Controller
Figure 8-28. I2C Acknowledgment
8.3.10.2.1.1 I2C Clock Stretching
The TPS25751A features clock stretching for the I2C protocol. The TPS25751A target I2C port can hold the clock
line (SCL) low after receiving (or sending) a byte, indicating that the bus is not yet ready to process more data.
The controller communicating with the target must not finish the transmission of the current bit and must wait
until the clock line actually goes high. When the target is clock stretching, the clock line remains low.
TPS25751A
SLVSJG7 – MAY 2026
www.ti.com
46
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Product Folder Links: TPS25751A



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