ADMV4530 datasheet(30/64 Pages) AD

30 / 64 page

Data Sheet

ADMV4530

THEORY OF OPERATION

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Rev. C | 30 of 64

The ADMV4530 integrates a fractional-N PLL, VCO, internal 2×

multiplier, and I/Q mixer. The fractional-N PLL locks the VCO to

a precise reference input signal for low noise operation. The VCO

signal is then multiplied by the internal 2× multiplier to generate the

necessary LO signal for the I/Q mixer. The I/Q mixer can operate

with either differential baseband I/Q inputs or a single-ended IF

input. The functionality of the various blocks within the ADMV4530

follows within this section.

SPI CONFIGURATION

The SPI of the ADMV4530 allows configuration of the device for

specific functions or operations via the 4-pin SPI port. This interface

provides users with added flexibility and customization. The SPI

consists of four control lines: SCLK, SDI, SDO, and CS. The

ADMV4530 protocol consists of a write/read bit followed by 15

field are organized MSB first and end with the LSB.

For a write operation, set the MSB to 0, and for a read operation,

set the MSB to 1. The write cycle must be sampled on the rising

edge of SCLK. The 24 bits of the serial write address and data are

shifted in on the SDI control line, MSB to LSB. The ADMV4530

input logic level for the write cycle supports a 3.3 V interface.

For a read cycle, the R/W bit and the 15 bits of address shift in

on the rising edge of SCLK on the SDI control line. Then, 8 bits of

serial read data shift out on the SDO control line, MSB first, on the

falling edge of SCLK. The output logic level for a read cycle is 3.3 V.

The output drivers of the SDO are enabled after the last rising edge

of SCLK of the instruction cycle and remain active until the end of

the read cycle. In a read operation, when CS is deasserted, SDO

returns to high impedance until the next read transaction. The CS is

active low and must be deasserted at the end of the write or read

sequence.

An active low input on CS starts and gates a communication

cycle. The CS pin allows more than one device to be used on the

same serial communications lines. The SDO pin goes to a high

impedance state when the CS input is high. During the communica-

tion cycle, the chip select must stay low. The SPI communications

protocol follows the Analog Devices, Inc., SPI standard. For more

information, see the ADI-SPI Serial Control Interface Standard (Rev

1.0).

The ADMV4530 consists of three register map sections. The first

section spans from Register 0x000 through Register 0x00D and

follows the standard Analog Devices SPI protocol, which includes

protocol setup and device identification registers. The second regis-

ter map section starts at Register 0x010 through Register 0x07C

and contains all of the relevant PLL control registers. The third reg-

ister map section starts at Register 0x100 through Register 0x119

and contains all of the mixer and baseband control registers. To

read back the register values from the first and third sections, the

REG_PAGE_SEL bits in Register 0x117 must be set to 1, and

to read back from the PLL section, the REG_PAGE_SEL bits in

DOUBLE BUFFERED REGISTERS

The PLL inside the ADMV4530 contains several double buffered

bit fields that take effect only after a write to the lower portion of

the N counter integer value (Register 0x010). This register applies

any changes to these double buffered bit fields and initiates the

autocalibration routine. The following is a list of the double buffered

bit fields and their corresponding registers:

►

REF_X2_EN (Register 0x022)

►

RDIV2 (Register 0x022)

►

R_WORD (Register 0x01F)

►

CP_CURRENT (Register 0x01E)

►

FRAC2WORD (Register 0x017 and Register 0x018)

►

FRAC1WORD (Register 0x014 through Register 0x017)

►

MOD2WORD (Register 0x019 and Register 0x01A)

►

BIT_INTEGER_WORD (Register 0x010 and Register 0x011)

START-UP INITIALIZATION SEQUENCE

Upon powering up or resetting the ADMV4530, it is recommended

to program the register map in reverse order, starting with the

highest register number first. The reverse order ensures that the

double buffered registers are programmed prior to initiating the

autocalibration routine and that all PLL control settings are in their

correct state. The recommended values of each register are shown

in both the Register Summary section and the Register Details

section. The following describes the recommended programming

sequence:

1. Program Register 0x000 to a value of 0x18 to enable the SDO

pin.

2. Program Register 0x117 to a value of 0x4C to enable reading

from the mixer section of the register map.

3. Program Register 0x100 through Register 0x119 in reverse or-

der based upon the desired mixer settings.

4. Program Register 0x117 to a value of 0x0C to enable reading

from the PLL section of the register map.

5. Program Register 0x010 through Register 0x07C in reverse or-

der based upon the desired PLL settings.

FREQUENCY UPDATE SEQUENCE

After the initialization sequence is performed, the output frequency

can be updated by programming Register 0x010 through Register

0x01A in reverse order.

ADMV4530 Datasheet(PDF) 30 Page - Analog Devices

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