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ADMV4530 Datasheet(PDF) 40 Page - Analog Devices |
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ADMV4530 Datasheet(HTML) 40 Page - Analog Devices |
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40 / 64 page  Data Sheet ADMV4530 REGISTER SUMMARY analog.com Rev. C | 40 of 64 N/A means not applicable, R means read, and R/W means read/write. Table 9. Register Summary Reg (Hex) Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Recommended R/W 000 REG0000 [7:0] SOFT_ RESET_R LSB_FIRST _R ADDR_ ASCN_ R SDO_ ACTIVE_R SDO_ ACTIVE ADDR_ ASCN LSB_FIRST SOFT_ RESET 0x00 0x18 R/W 001 REG0001 [7:0] SINGLE_ INSTRUC- TION CSB_ STALL CONTR OLLER _TARG ET_RB RESERVED 0x00 0x00 R/W 003 REG0003 [7:0] RESERVED CHIP_TYPE 0x01 N/A R 004 REG0004 [7:0] PRODUCT_ID[7:0] 0x21 N/A R 005 REG0005 [7:0] PRODUCT_ID[15:8] 0x00 N/A R 00A REG000A [7:0] SCRATCH_PAD 0x00 User defined R/W 00B REG000B [7:0] SPI_REV 0x01 N/A R 00C REG000C [7:0] VENDOR_ID[7:0] 0x56 N/A R 00D REG000D [7:0] VENDOR_ID[15:8] 0x04 N/A R 010 REG0010 [7:0] BIT_INTEGER_WORD[7:0] 0x80 User defined R/W 011 REG0011 [7:0] BIT_INTEGER_WORD[15:8] 0x00 User defined R/W 012 REG0012 [7:0] RESERVED AUTOCAL_ EN PRE_ SEL RESERVED 0x00 User defined R/W 014 REG0014 [7:0] FRAC1WORD[7:0] 0x00 User defined R/W 015 REG0015 [7:0] FRAC1WORD[15:8] 0x00 User defined R/W 016 REG0016 [7:0] FRAC1WORD[23:16] 0x00 User defined R/W 017 REG0017 [7:0] FRAC2WORD[6:0] FRAC1WO RD[24] 0x00 User defined R/W 018 REG0018 [7:0] RESERVED FRAC2WORD[13:7] 0x00 User defined R/W 019 REG0019 [7:0] MOD2WORD[7:0] 0x00 User defined R/W 01A REG001A [7:0] RESERVED MOD2WORD[13:8] 0x00 User defined R/W 01B REG001B [7:0] PHASE_WORD[7:0] 0x00 0x09 R/W 01C REG001C [7:0] PHASE_WORD[15:8] 0x00 0x00 R/W 01D REG001D [7:0] PHASE_WORD[23:16] 0x00 0x80 R/W 01E REG001E [7:0] CP_CURRENT PD_POL PLL_PD RESERVED CNTR_ RESET 0x00 2.1 mA: 0x58, 4.2 mA: 0xB8 R/W 01F REG001F [7:0] RESERVED R_WORD 0x00 ≥0x01 R/W 020 REG0020 [7:0] MUXOUT MUXOUT_ SEL MUXOUT_ LEV_SEL RESERVED 0x00 Data: 0x14, mux: 0x1C R/W 022 REG0022 [7:0] RESERVED REF_ X2_EN RDIV2 RESERVED 0x00 User defined R/W 025 REG0025 [7:0] RESERVED VCO_POUT_SEL 0x00 0x03 R/W 026 REG0026 [7:0] CP_BLEED 0x00 0x73 R/W 027 REG0027 [7:0] LD_BIAS LDP CP_BLEED _GATE CP_BLEED _EN VCO_PD RF_PBS 0x00 FRAC: 0xC9, INT: 0xE1 R/W 028 REG0028 [7:0] RESERVED LD_COUNT LOL_EN 0x00 0x03 R/W 02A REG002A [7:0] RESERVED CP_ BLEED _POL RESERVED CSB_SYNC RESERVED 0x00 0x00 R/W 02B REG002B [7:0] RESERVED LSB_P1 VAR_MOD_ EN RESERVED SD_MASK_ RESET_EN RESERVED SD_PD 0x00 FRAC: 0x10, INT: 0x01 R/W |
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