ADMV4530 datasheet(35/64 Pages) AD

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Data Sheet

ADMV4530

THEORY OF OPERATION

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Rev. C | 35 of 64

SYNTHESIZER LOCK TIMEOUT

The synthesizer lock timeout ensures that the VCO calibration digi-

tal-to-analog converter (DAC), which forces the VCO tune voltage

(VVTUNE), has settled to a steady value for the band select circuitry.

The SYNTH_LOCK_TIMEOUT and the TIMEOUT bits select the

length of time the DAC is allowed to settle to the final voltage before

the VCO calibration process continues to the next phase (VCO

band selection). The PFD frequency is the clock for this logic, and

the duration is set by using the following equation:

(SYNTH_LOCK_TIMEOUT × 1024 + TIMEOUT)/fPFD

(15)

where:

SYNTH_LOCK_TIMEOUT is programmed in Bits[4:0], Register

0x033.

TIMEOUT is programmed in Bits[7:0], Register 0x031 and Bits[1:0],

The calculated time must be greater than or equal to 20 µs.

For the SYNTH_LOCK_TIMEOUT bits, the minimum value is 2, and

the maximum value is 31.

For TIMEOUT, the minimum value is 2, and the maximum value is

1023.

VCO BAND SELECTION TIME

Use the VCO_BAND_DIV bits (Bits[7:0], Register 0x030) and the

fPFD to generate the VCO band selection clock (fBSC) as follows:

fBSC = (fPFD/VCO_BAND_DIV)

(16)

The calculated frequency must be less than 2.4 MHz.

Note that 16 clock cycles are required for one VCO core and band

calibration step and the total band selection process takes 11 steps,

resulting in the following equation:

11 × (16 × VCO_BAND_DIV/fPFD)

(17)

The minimum value for VCO_BAND_DIV is 1, and the maximum

value is 255.

PLL SETTLING TIME

The time taken for the loop to settle is inversely proportional to the

low-pass filter bandwidth.

CHIP TEMPERATURE READ BACK

Chip temperature readback can provide information regarding sys-

tem temperature, which is useful for system compensation.

The ADMV4530 includes an analog-to-digital converter (ADC) that

enables reading the chip temperature. The ADC clock (ADC_CLK)

is generated from the phase frequency detector clock (fPFD) with the

following equations:

ADC_CLK= fPFD

ADC_CLK_DIV × 4 + 2

(18)

where ADC_CLK_DIV is stored in Register 0x035.

A valid reference signal is required to complete a conversion.

Target 100 kHz for ADC_CLK and calculate ADC_CLK_DIV with

the following equation:

ADC_CLK_DIV = ceiling fPFD100,000– 24 (19)

If ADC_CLK_DIV is greater than 255, set these bits to 255.

The bits used for temperature readback are the following:

►

To read back the temperature, take the following steps:

1. Set ADC_ENABLE = 1 to enable the ADC.

2. Set ADC_CONVERSION = 1 to perform an ADC conversion.

3. Wait 16 ADC_CLK cycles.

4. Set VCO_FSM_READBACK = 101 (skip this step if it is already

set).

5. Read the VCO_DATA_READBACK bits in Register 0x06E to

read back the raw ADC output that corresponds to the chip

temperature (RAW_TEMP).

6. Set ADC_CONVERSION = 0 to disable the conversion.

7. Set ADC_ENABLE = 0 to disable the ADC, which pre-

vents any spurs generated by the ADC clock. Similarly, the

ADC_CLK_DISABLE bit can disable the ADC clock.

Perform Step 1 and Step 2 separately. However, Step 6 and Step 7

can be completed together.

To calculate the approximate chip temperature in Celsius (°C), use

the following equation:

Chip Temperature = −115°C + RAW_TEMP

(20)

RF OUTPUT DRIVER

As shown in the functional block diagram (see Figure 1), the

ADMV4530 incorporates two driver stages along with a voltage

variable attenuator (VVA) in the RF output section of the chip. The

VCTR_RF pin (Pin 4) is connected to the VVA, which adjusts the

RF output gain. The voltage range for the VCTR_RF pin is 0 V to

1.8 V, with a positively sloping linear region between 0.6 V to 1.5

V, as shown in Figure 8. The typical slope within linear region is 32

dB/V.

ADMV4530 Datasheet(PDF) 35 Page - Analog Devices

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