ADMV4530 datasheet(53/64 Pages) AD

53 / 64 page

Data Sheet

ADMV4530

analog.com

Rev. C | 53 of 64

Address: 0x02B, Reset: 0x00, Name: REG002B

Table 41. Bit Descriptions for REG002B

Bits

Bit Name

Description

Reset

Recommended

Access

[7:6]

RESERVED

Reserved.

0x0

R/W

LSB_P1

Add Half Bit to LSB of FRAC1 (when VAR_MOD_EN = 0).

0x0

R/W

0: disable.

1: enable.

VAR_MOD_EN

Auxiliary SDM Enable.

0x0

FRAC: 0x1, INT: 0x0

R/W

0: disable (FRAC2 = 0).

1: enable (FRAC2 ≠ 0).

RESERVED

Reserved.

0x0

R/W

SD_MASK_RESET_EN

SD Mask Reset Enable (When Updating REG0010).

0x0

R/W

0: disable.

1: enable.

RESERVED

Reserved.

0x0

R/W

SD_PD

Sigma Delta Power Down. Set this bit if FRAC1 = FRAC2 = 0.

0x0

FRAC: 0x0, INT: 0x1

R/W

0: power up (FRAC mode).

1: power down (INT mode).

Address: 0x02C, Reset: 0x00, Name: REG002C

Table 42. Bit Descriptions for REG002C

Bits

Bit Name

Description

Reset

Recommended

Access

[7:1]

RESERVED

Reserved.

0x0

R/W

DISABLE_ALC

VCO Automatic Level Control (ALC). Keep this bit set to 1.

0x0

0x1

R/W

0: enable.

1: disable.

Address: 0x030, Reset: 0x00, Name: REG0030

ADMV4530 Datasheet(PDF) 53 Page - Analog Devices

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