C167CS datasheet(26/517 Pages) INFINEON

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C167CS

Derivatives

Architectural Overview

User’s Manual

2-9

V2.0, 2000-07

The CPU has an actual register context consisting of up to 16 wordwide and/or bytewide

GPRs at its disposal, which are physically located within the on-chip RAM area. A

Context Pointer (CP) register determines the base address of the active register bank to

be accessed by the CPU at a time. The number of register banks is only restricted by the

available internal RAM space. For easy parameter passing, a register bank may overlap

others.

A system stack of up to 1536 words is provided as a storage for temporary data. The

system stack is also located within the on-chip RAM area, and it is accessed by the CPU

via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are

implicitly compared against the stack pointer value upon each stack access for the

detection of a stack overflow or underflow.

Hardware detection of the selected memory space is placed at the internal memory

decoders and allows the user to specify any address directly or indirectly and obtain the

desired data without using temporary registers or special instructions.

An 8 KByte 16-bit Wide on-chip XRAM (arranged in two blocks of 2 KByte and

6 KByte) provides fast access to user data (variables), user stacks and code. The on-

chip XRAM is realized as an X-Peripheral and appears to the software as an external

RAM. Therefore it cannot store register banks and is not bitaddressable. The XRAM

allows 16-bit accesses with maximum speed.

For Special Function Registers 1024 Bytes of the address space are reserved. The

standard Special Function Register area (SFR) uses 512 Bytes, while the Extended

Special Function Register area (ESFR) uses the other 512 Bytes. (E)SFRs are wordwide

registers which are used for controlling and monitoring functions of the different on-chip

units. Unused (E)SFR addresses are reserved for future members of the C166 Family

with enhanced functionality.

An Optional Internal ROM (32 KByte) provides for both code and constant data

storage. This memory area is connected to the CPU via a 32-bit-wide bus. Thus, an

entire double-word instruction can be fetched in just one machine cycle.

Program execution from on-chip program memory is the fastest of all possible

alternatives.

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