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C167CS Datasheet(PDF) 100 Page - Infineon Technologies AG |
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C167CS Datasheet(HTML) 100 Page - Infineon Technologies AG |
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100 / 517 page ![]() C167CS Derivatives Interrupt and Trap Functions User’s Manual 5-17 V2.0, 2000-07 The example below establishes 3 interrupt classes which cover 2 or 3 interrupt priorities, depending on the number of members in a class. A level 6 interrupt disables all other sources in class 2 by changing the current CPU level to 8, which is the highest priority (ILVL) in class 2. Class 1 requests or PEC requests are still serviced in this case. The 24 interrupt sources (excluding PEC requests) are so assigned to 3 classes of priority rather than to 7 different levels, as the hardware support would do. Table 5-6 Software Controlled Interrupt Classes (Example) ILVL (Priority) GLVL Interpretation 3210 15 PEC service on up to 8 channels 14 13 12 XXXXInterrupt Class 1 5 sources on 2 levels 11 X 10 9 8 XXXXInterrupt Class 2 9 sources on 3 levels 7 XXXX 6X 5 XXXXInterrupt Class 3 5 sources on 2 levels 4X 3 2 1 0 No service! |
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