C167CS datasheet(101/517 Pages) INFINEON

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C167CS

Derivatives

Interrupt and Trap Functions

User’s Manual

5-18

V2.0, 2000-07

5.4

Saving the Status During Interrupt Service

Before an interrupt request that has been arbitrated is actually serviced, the status of the

current task is automatically saved on the system stack. The CPU status (PSW) is saved

along with the location, where the execution of the interrupted task is to be resumed after

returning from the service routine. This return location is specified through the Instruction

Pointer (IP) and, in case of a segmented memory model, the Code Segment Pointer

(CSP). Bit SGTDIS in register SYSCON controls, how the return location is stored.

The system stack receives the PSW first, followed by the IP (unsegmented) or followed

by CSP and then IP (segmented mode). This optimizes the usage of the system stack,

if segmentation is disabled.

The CPU priority field (ILVL in PSW) is updated with the priority of the interrupt request

that is to be serviced, so the CPU now executes on the new level. If a multiplication or

division was in progress at the time the interrupt request was acknowledged, bit MULIP

in register PSW is set to ‘1’. In this case the return location that is saved on the stack is

not the next instruction in the instruction flow, but rather the multiply or divide instruction

itself, as this instruction has been interrupted and will be completed after returning from

the service routine.

Figure 5-3

Task Status Saved on the System Stack

The interrupt request flag of the source that is being serviced is cleared. The IP is loaded

with the vector associated with the requesting source (the CSP is cleared in case of

segmentation) and the first instruction of the service routine is fetched from the

respective vector location, which is expected to branch to the service routine itself. The

data page pointers and the context pointer are not affected.

When the interrupt service routine is left (RETI is executed), the status information is

popped from the system stack in the reverse order, taking into account the value of bit

SGTDIS.

(Unsegmented)

PSW

System Stack after

Interrupt Entry

System Stack before

High

Addresses

Low

Addresses

MCD02226

Interrupt Entry

System Stack after

(Segmented)

Task

Interrupted

Status of

CSP

PSW

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