C167CS datasheet(60/517 Pages) INFINEON

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C167CS

Derivatives

The Central Processing Unit (CPU)

User’s Manual

4-10

V2.0, 2000-07

4.3

Bit-Handling and Bit-Protection

The C167CS provides several mechanisms to manipulate bits. These mechanisms

either manipulate software flags within the internal RAM, control on-chip peripherals via

control bits in their respective SFRs or control IO functions via port pins.

The instructions BSET, BCLR, BAND, BOR, BXOR, BMOV, BMOVN explicitly set or

clear specific bits. The instructions BFLDL and BFLDH allow to manipulate up to 8 bits

of a specific byte at one time. The instructions JBC and JNBS implicitly clear or set the

specified bit when the jump is taken. The instructions JB and JNB (also conditional jump

instructions that refer to flags) evaluate the specified bit to determine if the jump is to be

taken.

Note: Bit operations on undefined bit locations will always read a bit value of ‘0’, while

the write access will not effect the respective bit location.

All instructions that manipulate single bits or bit groups internally use a read-modify-write

sequence that accesses the whole word, which contains the specified bit(s).

This method has several consequences:

• Bits can only be modified within the internal address areas, i.e. internal RAM and

SFRs. External locations cannot be used with bit instructions.

The upper 256 Bytes of the SFR area, the ESFR area and the internal RAM are bit-

addressable (see Chapter 3), i.e. those register bits located within the respective

sections can be directly manipulated using bit instructions. The other SFRs must be

accessed byte/word wise.

Note: All GPRs are bit-addressable independent of the allocation of the register bank via

the context pointer CP. Even GPRs which are allocated to not bit-addressable

RAM locations provide this feature.

• The read-modify-write approach may be critical with hardware-effected bits. In these

cases the hardware may change specific bits while the read-modify-write operation is

in progress, where the writeback would overwrite the new bit value generated by the

hardware. The solution is either the implemented hardware protection (see below) or

realized through special programming (see Chapter 4.2).

Protected bits are not changed during the read-modify-write sequence, i.e. when

hardware sets e.g. an interrupt request flag between the read and the write of the read-

modify-write sequence. The hardware protection logic guarantees that only the intended

bit(s) is/are effected by the write-back operation.

Note: If a conflict occurs between a bit manipulation generated by hardware and an

intended software access the software access has priority and determines the

final value of the respective bit.

A summary of the protected bits implemented in the C167CS can be found at the end of

Chapter 2.

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