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C167CS

Derivatives

The Central Processing Unit (CPU)

User’s Manual

4-4

V2.0, 2000-07

Sequential Instruction Processing

Each single instruction has to pass through each of the four pipeline stages regardless

of whether all possible stage operations are really performed or not. Since passing

through one pipeline stage takes at least one machine cycle, any isolated instruction

takes at least four machine cycles to be completed. Pipelining, however, allows parallel

(i.e. simultaneous) processing of up to four instructions. Thus, most of the instructions

seem to be processed during one machine cycle as soon as the pipeline has been filled

once after reset (see Figure 4-2).

Instruction pipelining increases the average instruction throughput considered over a

certain period of time. In the following, any execution time specification of an instruction

always refers to the average execution time due to pipelined parallel instruction

processing.

Figure 4-2

Sequential Instruction Pipelining

Standard Branch Instruction Processing

Instruction pipelining helps to speed sequential program processing. In the case that a

branch is taken, the instruction which has already been fetched providently is mostly not

the instruction which must be decoded next. Thus, at least one additional machine cycle

is normally required to fetch the branch target instruction. This extra machine cycle is

provided by means of an injected instruction (see Figure 4-3).

Figure 4-3

Standard Branch Instruction Pipelining

MCT04327

FETCH

DECODE

EXECUTE

WRITEBACK

1 Machine Cycle

Time

MCT04328

FETCH

DECODE

EXECUTE

WRITEBACK

BRANCH

n+2

TARGET

(

INJECT)

1 Machine Cycle

Time

BRANCH

...

TARGET+1

TARGET

(

INJECT)

TARGET+2

TARGET+1

(

INJECT)

TARGET

TARGET+2

TARGET+1

TARGET

TARGET+3

Injection

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