C167CS datasheet(57/517 Pages) INFINEON

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C167CS

Derivatives

The Central Processing Unit (CPU)

User’s Manual

4-7

V2.0, 2000-07

Explicit Stack Pointer Updating

None of the RET, RETI, RETS, RETP or POP instructions is capable of correctly using

a new SP register value, which is to be updated by an immediately preceding instruction.

Thus, in order to use the new SP register value without erroneously performed stack

accesses, at least one instruction must be inserted between an explicitly SP-writing and

any subsequent of the just mentioned implicitly SP-using instructions, as shown in the

following example:

:MOV SP,#0FA40H

;select a new top of stack

In + 1:…

;must not be an instruction popping operands

;from the system stack

In + 2:POP R0

;pop word value from new top of stack

;into R0

Note: Conflicts with instructions writing to the stack (PUSH, CALL, SCXT) are solved

internally by the CPU logic.

Controlling Interrupts

Software modifications (implicit or explicit) of the PSW are done in the execute phase of

the respective instructions. In order to maintain fast interrupt responses, however, the

current interrupt prioritization round does not consider these changes, i.e. an interrupt

request may be acknowledged after the instruction that disables interrupts via IEN or

ILVL or after the following instructions. Timecritical instruction sequences therefore

should not begin directly after the instruction disabling interrupts, as shown in the

following examples:

INTERRUPTS_OFF:

BCLR IEN

;globally disable interrupts

;non-critical instruction

;begin of uninterruptable critical sequence

…

;end of uninterruptable critical sequence

INTERRUPTS_ON:

BSET IEN

;globally re-enable interrupts

CRITICAL_SEQUENCE:

ATOMIC #3

;immediately block interrupts

BCLR IEN

;globally disable interrupts

…

;here is the uninterruptable sequence

BSET IEN

;globally re-enable interrupts

Note: The described delay of 1 instruction also applies for enabling the interrupts system

i.e. no interrupt requests are acknowledged until the instruction following the

enabling instruction.

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