C167CS datasheet(40/517 Pages) INFINEON

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C167CS

Derivatives

Memory Organization

User’s Manual

3-3

V2.0, 2000-07

3.1

Internal ROM Area

The C167CS may reserve an address area of variable size (depending on the version)

for on-chip mask-programmable ROM/Flash/OTP memory (organized as X

× 32). The

lower 32 KByte of this on-chip memory block are referred to as “Internal ROM Area”.

Internal ROM accesses are globally enabled or disabled via bit ROMEN in register

SYSCON. This bit is set during reset according to the level on pin EA, or may be altered

via software. If enabled, the internal ROM area occupies the lower 32 KByte of either

segment 0 or segment 1 (alternate ROM area). This mapping is controlled by bit ROMS1

in register SYSCON.

Note: The size of the internal ROM area is independent of the size of the actual

implemented Program Memory. Also devices with less than 32 KByte of Program

Memory or with no Program Memory at all will have this 32 KByte area occupied,

if the Program Memory is enabled. Devices with a larger Program Memory provide

the mapping option only for the internal ROM area.

Devices with a Program Memory size above 32 KByte expand the ROM area from the

middle of segment 1, i.e. starting at address 01’8000H.

The internal Program Memory can be used for both code (instructions) and data

(constants, tables, etc.) storage.

Code fetches are always made on even byte addresses. The highest possible code

storage location in the internal Program Memory is either xx’xxFEH for single word

instructions, or xx’xxFCH for double word instructions. The respective location must

contain a branch instruction (unconditional), because sequential boundary crossing from

internal Program Memory to external memory is not supported and causes erroneous

results.

Any word and byte data read accesses may use the indirect or long 16-bit addressing

modes. There is no short addressing mode for internal ROM operands. Any word data

access is made to an even byte address. The highest possible word data storage

location in the internal ROM is xx’xxFEH. For PEC data transfers the internal Program

Memory can be accessed independent of the contents of the DPP registers via the PEC

source and destination pointers.

The internal Program Memory is not provided for single bit storage, and therefore it is

not bit addressable.

Note: The ‘x’ in the locations above depend on the available Program Memory and on

the mapping.

The internal ROM may be enabled, disabled or mapped into segment 0 or segment 1

under software control. Chapter 22 shows how to do this and reminds of the precautions

that must be taken in order to prevent the system from crashing.

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