C167CS datasheet(93/517 Pages) INFINEON

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C167CS

Derivatives

Interrupt and Trap Functions

User’s Manual

5-10

V2.0, 2000-07

Interrupt Control Functions in the PSW

The Processor Status Word (PSW) is functionally divided into 2 parts: the lower byte of

the PSW basically represents the arithmetic status of the CPU, the upper byte of the

PSW controls the interrupt system of the C167CS and the arbitration mechanism for the

external bus interface.

Note: Pipeline effects have to be considered when enabling/disabling interrupt requests

via modifications of register PSW (see Chapter 4).

PSW

Processor Status Word

SFR (FF10H/88H)

Reset Value: 0000H

98765

43210

ILVL

IEN

HLD

USR

MUL

EZV

rwh

Bit

Function

N, C, V, Z, E,

MULIP, USR0

CPU status flags (Described in Chapter 4)

Define the current status of the CPU (ALU, multiplication unit).

HLDEN

HOLD Enable (Enables External Bus Arbitration)

Bus arbitration disabled,

P6.7 … P6.5 may be used for general purpose IO

Bus arbitration enabled,

P6.7 … P6.5 serve as BREQ, HLDA, HOLD, resp.

IEN

Interrupt Enable Control Bit (Globally enables/disables interrupt

requests)

Interrupt requests are disabled

Interrupt requests are enabled

ILVL

CPU Priority Level

Defines the current priority level for the CPU

FH:

Highest priority level

0H:

Lowest priority level

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