C167CS datasheet(31/517 Pages) INFINEON

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C167CS

Derivatives

Architectural Overview

User’s Manual

2-14

V2.0, 2000-07

The On-Chip CAN Modules

The integrated CAN Modules (CAN1, CAN2) handle the completely autonomous

transmission and reception of CAN frames in accordance with the CAN specification

V2.0 part B (active), i.e. the on-chip CAN Module can receive and transmit standard

frames with 11-bit identifiers as well as extended frames with 29-bit identifiers.

The modules provide Full CAN functionality on up to 15 message objects (up to

30 objects if both modules are connected to the same physical bus). Message object 15

may be configured for Basic CAN functionality. Both modes provide separate masks for

acceptance filtering which allows to accept a number of identifiers in Full CAN mode and

also allows to disregard a number of identifiers in Basic CAN mode. All message objects

can be updated independent from the other objects and are equipped for the maximum

message length of 8 Bytes.

The bit timing is derived from the XCLK and is programmable up to a data rate of

1 MBaud. Each CAN Module uses two pins (configurable, both modules may use the

same pair of pins) to interface to a bus transceiver.

Parallel Ports

The C167CS provides up to 111 IO lines which are organized into eight input/output

ports and one input port. All port lines are bit-addressable, and all input/output lines are

individually (bit-wise) programmable as inputs or outputs via direction registers. The IO

ports are true bidirectional ports which are switched to high impedance state when

configured as inputs. The output drivers of six IO ports can be configured (pin by pin) for

push/pull operation or open-drain operation via control registers. During the internal

reset, all port pins are configured as inputs.

All port lines have programmable alternate input or output functions associated with

them. PORT0 and PORT1 may be used as address and data lines when accessing

external memory, while Port 4 outputs the additional segment address bits A23/19/17 …

A16 in systems where segmentation is used to access more than 64 KBytes of memory.

Port 6 provides the optional bus arbitration signals (BREQ, HLDA, HOLD) and the chip

select signals CS4 … CS0. Port 2 accepts the fast external interrupt inputs and provides

inputs/outputs for the CAPCOM1 unit. Port 3 includes alternate functions of timers, serial

interfaces, the optional bus control signal BHE, and the system clock output (CLKOUT/

FOUT). Port 5 is used for timer control signals and for the analog inputs to the A/D

Converter. The analog extension channels are connected via P1L. Port 7 provides the

output signals from the PWM unit and inputs/outputs for the CAPCOM2 unit (more on

P1H). Port 8 provides inputs/outputs for the CAPCOM2 unit. Four pins of PORT1 may

also be used as inputs/outputs for the CAPCOM2 unit. All port lines that are not used for

these alternate functions may be used as general purpose IO lines.

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