C167CS datasheet(90/517 Pages) INFINEON

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C167CS

Derivatives

Interrupt and Trap Functions

User’s Manual

5-7

V2.0, 2000-07

The Interrupt Request Flag is set by hardware whenever a service request from the

respective source occurs. It is cleared automatically upon entry into the interrupt service

routine or upon a PEC service. In the case of PEC service the Interrupt Request flag

remains set, if the COUNT field in register PECCx of the selected PEC channel

decrements to zero. This allows a normal CPU interrupt to respond to a completed PEC

block transfer.

Note: Modifying the Interrupt Request flag via software causes the same effects as if it

had been set or cleared by hardware.

The Interrupt Enable Control Bit determines whether the respective interrupt node

takes part in the arbitration cycles (enabled) or not (disabled). The associated request

flag will be set upon a source request in any case. The occurrence of an interrupt request

can so be polled via xxIR even while the node is disabled.

Note: In this case the interrupt request flag xxIR is not cleared automatically but must be

cleared via software.

xxIC

(E)SFR (yyyyH/zzH)

Reset Value: - - 00H

9876

543210

xxIR xxIE

ILVL

GLVL

rwh

Bit

Function

GLVL

Group Level

Defines the internal order for simultaneous requests of the same priority.

Highest group priority

Lowest group priority

ILVL

Interrupt Priority Level

Defines the priority level for the arbitration of requests.

FH:

Highest priority level

0H:

Lowest priority level

xxIE

Interrupt Enable Control Bit (individually enables/disables a specific source)

‘0’:

Interrupt request is disabled

‘1’:

Interrupt Request is enabled

xxIR

Interrupt Request Flag

‘0’:

No request pending

‘1’:

This source has raised an interrupt request

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